On Tue, Feb 19, 2013 at 03:59:16PM -0800, Ben Widawsky wrote: > On Thu, Feb 14, 2013 at 02:46:44PM -0800, Ben Widawsky wrote: > > On Thu, Feb 14, 2013 at 09:53:51PM +0200, ville.syrjala at linux.intel.com wrote: > > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > > > The bit controlling whether PIPE_CONTROL DW/QW write targets > > > the global GTT or PPGTT moved moved from DW 2 bit 2 to > > > DW 1 bit 24 on IVB. > > > > > > I verified on IVB that the fix is in fact effective. Without the fix > > > none of the scratch writes actually landed in the pipe control page. > > > With the fix the writes show up correctly. > > > > > > v2: move PIPE_CONTROL_GLOBAL_GTT_IVB setup to where other flags are set > > > > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > Reviewed-by: Ben Widawsky <ben at bwidawsk.net> > > [snip] > > Reading the bspec again... do we want to set bit 21? I don't think we want to do that. The scratch address we're using here is a proper GTT address, not an index into the HWS page. I have no idea why we're not using the HSW page here as well. I couldn't dig out any reason from the commit logs either. Anyone? -- Ville Syrj?l? Intel OTC
