✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)

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Title: Project List - Patchwork
Patch Details
Series:drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)
URL:https://patchwork.freedesktop.org/series/82173/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/index.html

CI Bug Log - changes from CI_DRM_9093 -> Patchwork_18620

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18620/index.html

Known issues

Here are the changes found in Patchwork_18620 that come from known issues:

IGT changes

Issues hit

Possible fixes

Warnings

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (45 -> 39)

Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus

Build changes

CI-20190529: 20190529
CI_DRM_9093: 827ebff930c6340ed1c1c274909717525951c496 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5798: 430bad5a53c08125fbd48978ed6a66f61a33a40b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18620: 77fe9153f15371efa976b7ebdb10e9a1df31054e @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

77fe9153f153 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
5eca404d0060 drm/i915: Add an encoder hook to sanitize its state during init/resume
99999f4fedb1 drm/i915: Check for unsupported DP link rates during initial commit
94f36ee39ef6 drm/i915: Move the initial fastset commit check to encoder hooks
f0622b209712 drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming

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