✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2)

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Title: Project List - Patchwork
Patch Details
Series:drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2)
URL:https://patchwork.freedesktop.org/series/82173/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18619/index.html

CI Bug Log - changes from CI_DRM_9093 -> Patchwork_18619

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18619/index.html

Known issues

Here are the changes found in Patchwork_18619 that come from known issues:

CI changes

IGT changes

Issues hit

Warnings

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (45 -> 39)

Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus

Build changes

CI-20190529: 20190529
CI_DRM_9093: 827ebff930c6340ed1c1c274909717525951c496 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5798: 430bad5a53c08125fbd48978ed6a66f61a33a40b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18619: 1f86980be6c9f250cace3c634b8f62a9fcc4d57b @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

1f86980be6c9 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
57989410859f drm/i915: Add an encoder hook to sanitize its state during init/resume
a5fbed9f3baa drm/i915: Check for unsupported DP link rates during initial commit
275ab3d8d970 drm/i915: Move the initial fastset commit check to encoder hooks
056e9d5d8a88 drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming

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