On Wed, Sep 30, 2020 at 10:20:41AM -0700, Matt Roper wrote:
On Tue, Sep 29, 2020 at 11:42:33PM -0700, Lucas De Marchi wrote:From: Anshuman Gupta <anshuman.gupta@xxxxxxxxx> DGFX devices have different DMC_DEBUG* counter MMIO address offset. Incorporate these changes in i915_reg.h for DG1 and handle i915_dmc_info accordingly. Cc: Uma Shankar <uma.shankar@xxxxxxxxx> Signed-off-by: Anshuman Gupta <anshuman.gupta@xxxxxxxxx> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx> --- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++-- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 0bf31f9a8af5..472f119fe246 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -518,8 +518,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused) CSR_VERSION_MINOR(csr->version)); if (INTEL_GEN(dev_priv) >= 12) { - dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; - dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; + if (IS_DG1(dev_priv)) {I think we'd want IS_DGFX here since this change should hold true for any future dgfx platform as well. Aside from that,
not sure where this info came from, but it's not true. Not having DC6 is not related to being DGFX an future platforms may as well support it.
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx> I notice the bspec does have a new DC6 residency register offset listed as well, which seems odd if we don't have DC6 support on this platform.
previous version of this patch was defining that but it's unused so I removed it. Lucas De Marchi
Matt+ dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; + } else { + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; + } + /* * NOTE: DMC_DEBUG3 is a general purpose reg. * According to B.Specs:49196 DMC f/w reuses DC5/6 counter diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bb5094b80f15..b856a1fb0a32 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7538,6 +7538,7 @@ enum { #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) +#define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154) #define DMC_DEBUG3 _MMIO(0x101090) -- 2.28.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx-- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795
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