✗ Fi.CI.BAT: failure for Introduce DG1

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Title: Project List - Patchwork
Patch Details
Series:Introduce DG1
URL:https://patchwork.freedesktop.org/series/82241/
State:failure
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18595/index.html

CI Bug Log - changes from CI_DRM_9077 -> Patchwork_18595

Summary

FAILURE

Serious unknown changes coming with Patchwork_18595 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18595, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18595/index.html

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_18595:

IGT changes

Possible regressions

Known issues

Here are the changes found in Patchwork_18595 that come from known issues:

IGT changes

Issues hit

Possible fixes

Warnings

Participating hosts (45 -> 38)

Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus

Build changes

CI-20190529: 20190529
CI_DRM_9077: ae1f3f7de609df105aeceed2655656ffc838d720 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5793: c34792447c9fc4d05dd75873cdb99d9ffe57ea23 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18595: b609cfe8808be834400aab6819a1b43b7bc5a5d8 @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

b609cfe8808b drm/i915/dgfx: define llc and snooping behaviour
648249c6dd8b drm/i915/dg1: Change DMC_DEBUG{1, 2} registers
9034c09bbbdf drm/i915/dg1: DG1 does not support DC6
01007b9c648c drm/i915/dg1: Add initial DG1 workarounds
f5c37ea500ef drm/i915/dg1: Load DMC
571405def6c9 drm/i915/dg1: enable PORT C/D aka D/E
3056c7ce001a drm/i915/dg1: map/unmap pll clocks
d0727f32e9ec drm/i915/dg1: provide port/phy mapping for vbt
dc3f763d7b05 drm/i915/dg1: Update voltage swing tables for DP
e764c35d3b9e drm/i915/dg1: Update comp master/slave relationships for PHYs
a96cb47a46d4 drm/i915/dg1: Don't program PHY_MISC for PHY-C and PHY-D
b5634537768e drm/i915/dg1: Enable first 2 ports for DG1
ed7812a70681 drm/i915/dg1: gmbus pin mapping
1556d9b840f8 drm/i915/dg1: invert HPD pins
4caa7e8d99ff drm/i915/dg1: add hpd interrupt handling
fc9e91e510d5 drm/i915/dg1: Enable DPLL for DG1
802098453f92 drm/i915/dg1: Add and setup DPLLs for DG1
46ba3b109500 drm/i915/dg1: Add DPLL macros for DG1
313e894b5c43 drm/i915/dg1: Wait for pcode/uncore handshake at startup
af7964472d1d drm/i915/dg1: Increase mmio size to 4MB
44b1fb34d9e6 drm/i915/dg1: Add DG1 power wells
90eb98d91e8e drm/i915/dg1: Define MOCS table for DG1
02a93e492718 drm/i915/dg1: Initialize RAWCLK properly
2ab727864817 drm/i915/dg1: add more PCI ids

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