✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock

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Title: Project List - Patchwork
Patch Details
Series:drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
URL:https://patchwork.freedesktop.org/series/82173/
State:success
Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18586/index.html

CI Bug Log - changes from CI_DRM_9068 -> Patchwork_18586

Summary

SUCCESS

No regressions found.

External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18586/index.html

Known issues

Here are the changes found in Patchwork_18586 that come from known issues:

IGT changes

Issues hit

Possible fixes

Warnings

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (46 -> 39)

Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus

Build changes

CI-20190529: 20190529
CI_DRM_9068: a41d308b2f54b33a4a90011f4fe16dc5ef7e49a1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5790: 722a3eb9734f04030508d244df9dff55c5ab686c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18586: 6520c445f2d425ceebd3b7e6e2eb3b3aa0d4c892 @ git://anongit.freedesktop.org/gfx-ci/linux

== Linux commits ==

6520c445f2d4 drm/i915/tgl: Add workaround for incorrect BIOS combo PHY DPLL programming
a6fb67e5b7e2 drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock
4be8359615d9 drm/i915/icl: Cross check the combo PLL WRPLL parameters wrt. hard-coded PLL freqs
a9de3d654f6f drm/i915: Factor out skl_wrpll_calc_freq()
885b445fa0a6 drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming

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