> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Ville
> Syrjala
> Sent: Friday, September 18, 2020 3:14 AM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH 3/3] drm/i915: Use the correct bpp when
> validating "4:2:0 only" modes
>
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> When validating a "YCbCr 4:2:0 only" mode we must take into account the
> fact that we're going to be outputting YCbCr
> 4:2:0 or 4:4:4 (when a DP->HDMI protocol converter is doing the 4:2:0
> downsampling). For YCbCr 4:4:4 the minimum output bpc is 8, for YCbCr 4:2:0
> it'll be half that. The currently hardcoded 6bpc is only correct for RGB 4:4:4,
> which we will never use with these kinds of modes. Figure out what we're
> going to output and use the correct min bpp value to validate whether the
> link has sufficient bandwidth.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
Thanks,
Vandita
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 55 +++++++++++++++----------
> 1 file changed, 33 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index aa4801a8123d..54a4b81ea3ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -608,6 +608,37 @@ intel_dp_output_format(struct drm_connector
> *connector,
> return INTEL_OUTPUT_FORMAT_YCBCR420;
> }
>
> +int intel_dp_min_bpp(enum intel_output_format output_format) {
> + if (output_format == INTEL_OUTPUT_FORMAT_RGB)
> + return 6 * 3;
> + else
> + return 8 * 3;
> +}
> +
> +static int intel_dp_output_bpp(enum intel_output_format output_format,
> +int bpp) {
> + /*
> + * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
> + * format of the number of bytes per pixel will be half the number
> + * of bytes of RGB pixel.
> + */
> + if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> + bpp /= 2;
> +
> + return bpp;
> +}
> +
> +static int
> +intel_dp_mode_min_output_bpp(struct drm_connector *connector,
> + const struct drm_display_mode *mode) {
> + enum intel_output_format output_format =
> + intel_dp_output_format(connector, mode);
> +
> + return intel_dp_output_bpp(output_format,
> +intel_dp_min_bpp(output_format)); }
> +
> static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
> int hdisplay)
> {
> @@ -687,7 +718,8 @@ intel_dp_mode_valid(struct drm_connector
> *connector,
> max_lanes = intel_dp_max_lane_count(intel_dp);
>
> max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
> - mode_rate = intel_dp_link_required(target_clock, 18);
> + mode_rate = intel_dp_link_required(target_clock,
> +
> intel_dp_mode_min_output_bpp(connector, mode));
>
> if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
> return MODE_H_ILLEGAL;
> @@ -2111,19 +2143,6 @@ intel_dp_adjust_compliance_config(struct
> intel_dp *intel_dp,
> }
> }
>
> -static int intel_dp_output_bpp(enum intel_output_format output_format,
> int bpp) -{
> - /*
> - * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
> - * format of the number of bytes per pixel will be half the number
> - * of bytes of RGB pixel.
> - */
> - if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> - bpp /= 2;
> -
> - return bpp;
> -}
> -
> /* Optimize link config in order: max bpp, min clock, min lanes */ static int
> intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, @@ -2346,14
> +2365,6 @@ static int intel_dp_dsc_compute_config(struct intel_dp
> *intel_dp,
> return 0;
> }
>
> -int intel_dp_min_bpp(enum intel_output_format output_format) -{
> - if (output_format == INTEL_OUTPUT_FORMAT_RGB)
> - return 6 * 3;
> - else
> - return 8 * 3;
> -}
> -
> static int
> intel_dp_compute_link_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> --
> 2.26.2
>
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