On Mon, 07 Sep 2020, Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> There's no real reason to stash away the DPIO PHY IOSF sideband port
> numbers for VLV/CHV. Just compute them at runtime in the sideband code.
>
> Gets rid of the oddball intel_init_dpio() function from the high level
> init flow.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Yes, please!
Reviewed-by: Jani Nikula <jani.nikula@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 2 --
> drivers/gpu/drm/i915/i915_drv.c | 16 ----------------
> drivers/gpu/drm/i915/i915_drv.h | 2 --
> drivers/gpu/drm/i915/i915_reg.h | 1 -
> drivers/gpu/drm/i915/intel_sideband.c | 16 ++++++++++++++--
> 5 files changed, 14 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 3670cabeb3cd..003b68dda944 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -272,8 +272,6 @@ enum dpio_phy {
> DPIO_PHY2,
> };
>
> -#define I915_NUM_PHYS_VLV 2
> -
> enum aux_ch {
> AUX_CH_A,
> AUX_CH_B,
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d66fe09d337e..94e00e450683 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -215,21 +215,6 @@ intel_teardown_mchbar(struct drm_i915_private *dev_priv)
> release_resource(&dev_priv->mch_res);
> }
>
> -static void intel_init_dpio(struct drm_i915_private *dev_priv)
> -{
> - /*
> - * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
> - * CHV x1 PHY (DP/HDMI D)
> - * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
> - */
> - if (IS_CHERRYVIEW(dev_priv)) {
> - DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
> - DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
> - } else if (IS_VALLEYVIEW(dev_priv)) {
> - DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
> - }
> -}
> -
> static int i915_workqueues_init(struct drm_i915_private *dev_priv)
> {
> /*
> @@ -358,7 +343,6 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> intel_detect_pch(dev_priv);
>
> intel_pm_setup(dev_priv);
> - intel_init_dpio(dev_priv);
> ret = intel_power_domains_init(dev_priv);
> if (ret < 0)
> goto err_gem;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index a455752221cc..ef75acda9bff 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1020,8 +1020,6 @@ struct drm_i915_private {
> */
> u8 active_pipes;
>
> - int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
> -
> struct i915_wa_list gt_wa_list;
>
> struct i915_frontbuffer_tracking fb_tracking;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ab4b1abd4364..90a05e37ba2f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1382,7 +1382,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define DPIO_CMNRST (1 << 0)
>
> #define DPIO_PHY(pipe) ((pipe) >> 1)
> -#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
>
> /*
> * Per pipe/PLL DPIO regs
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 916ccd1c0e96..5b3279262123 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -231,9 +231,21 @@ void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
> SB_CRWRDA_NP, reg, &val);
> }
>
> +static u32 vlv_dpio_phy_iosf_port(struct drm_i915_private *i915, enum dpio_phy phy)
> +{
> + /*
> + * IOSF_PORT_DPIO: VLV x2 PHY (DP/HDMI B and C), CHV x1 PHY (DP/HDMI D)
> + * IOSF_PORT_DPIO_2: CHV x2 PHY (DP/HDMI B and C)
> + */
> + if (IS_CHERRYVIEW(i915))
> + return phy == DPIO_PHY0 ? IOSF_PORT_DPIO_2 : IOSF_PORT_DPIO;
> + else
> + return IOSF_PORT_DPIO;
> +}
> +
> u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
> {
> - int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
> + u32 port = vlv_dpio_phy_iosf_port(i915, DPIO_PHY(pipe));
> u32 val = 0;
>
> vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
> @@ -252,7 +264,7 @@ u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
> void vlv_dpio_write(struct drm_i915_private *i915,
> enum pipe pipe, int reg, u32 val)
> {
> - int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
> + u32 port = vlv_dpio_phy_iosf_port(i915, DPIO_PHY(pipe));
>
> vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
> }
--
Jani Nikula, Intel Open Source Graphics Center
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