On Thu, Feb 14, 2013 at 05:51:24PM -0200, Paulo Zanoni wrote: > Hi > > 2012/12/18 Rodrigo Vivi <rodrigo.vivi at gmail.com>: > > On Tue, Dec 11, 2012 at 4:48 PM, Damien Lespiau > > <damien.lespiau at gmail.com> wrote: > >> FDI_RX_PLL_ENABLE > > I noticed that we have a restriction on PLL_ENABLE: > > "After enabling the FDI PLL, software must wait for a warmup period > > before enabling the link" > > > > warmup for this is 25us. > > Are we covered already with this 220 or should we increase it? > > I'm not sure. > > Yes. On the Haswell doc, mode set sequence for CRT: "Enable PCH FDI > Receiver PLL, wait 200 ?s for warmup plus 20 ?s DMI latency". > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com> Picked up the first patch of this series. Or does that r-b also how for the DDI patch in here? The 3rd one likely doesn't apply any more, and I don't really have an opinion about that particular bikeshed. -Daniel > > > > > Other than that, feel free to use > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com> > > > > > > > > > > > > -- > > Rodrigo Vivi > > Blog: http://blog.vivi.eng.br > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx at lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- > Paulo Zanoni > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
