Add an extra vblank before fbc is activated.
WA: 1409689360
Corruption with FBC around plane 1A enabling. In the Frame Buffer
Compression programming sequence "Display Plane Enabling with FBC"
add a wait for vblank between plane enabling step 1 and FBC enabling
step 2.
Signed-off-by: Uma Shankar <uma.shankar@xxxxxxxxx>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 2ab32e6532ff..0ed252ff2c53 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1085,10 +1085,12 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc)
if (!intel_fbc_can_activate(crtc))
return;
- if (!fbc->busy_bits)
+ if (!fbc->busy_bits) {
+ intel_wait_for_vblank(dev_priv, crtc->pipe);
intel_fbc_hw_activate(dev_priv);
- else
+ } else {
intel_fbc_deactivate(dev_priv, "frontbuffer write");
+ }
}
void intel_fbc_post_update(struct intel_atomic_state *state,
--
2.22.0
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