On Wed, 2020-08-05 at 18:00 +0300, Imre Deak wrote: > The command register is the low PCODE MBOX low register not the high > one as described by the spec. This left the system with the TC-cold > power state being blocked all the time. Fix things by using the correct > register. > > Also to make sure we retry a request for at least 600usec, when the > PCODE MBOX command itself succeeded, but the TC-cold block command > failed, sleep for 1msec unconditionally after any fail. > > The change was tested with JTAG register read of the HW/FW's actual > TC-cold state, which reported the expected states after this change. > Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > Tested-by: Nivedita Swaminathan < > nivedita.swaminathan@xxxxxxxxx > > > Cc: José Roberto de Souza < > jose.souza@xxxxxxxxx > > > Signed-off-by: Imre Deak < > imre.deak@xxxxxxxxx > > > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 10 +++++----- > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- > 2 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 9f0241a53a45..8f0b712ed7a0 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -3927,12 +3927,13 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block) > int ret; > > while (1) { > - u32 low_val = 0, high_val; > + u32 low_val; > + u32 high_val = 0; > > if (block) > - high_val = TGL_PCODE_EXIT_TCCOLD_DATA_H_BLOCK_REQ; > + low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ; > else > - high_val = TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ; > + low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ; > > /* > * Spec states that we should timeout the request after 200us > @@ -3951,8 +3952,7 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block) > if (++tries == 3) > break; > > - if (ret == -EAGAIN) > - msleep(1); > + msleep(1); > } > > if (ret) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 2b403df03404..e85c6fc1f3cb 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9226,8 +9226,8 @@ enum { > #define DISPLAY_IPS_CONTROL 0x19 > #define TGL_PCODE_TCCOLD 0x26 > #define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0) > -#define TGL_PCODE_EXIT_TCCOLD_DATA_H_BLOCK_REQ 0 > -#define TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ REG_BIT(0) > +#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0 > +#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0) > /* See also IPS_CTL */ > #define IPS_PCODE_CONTROL (1 << 30) > #define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx