On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote: > From: Anshuman Gupta < > anshuman.gupta@xxxxxxxxx > > > > DC6 is not supported on DG1, so change the allowed DC mask for DG1. > > Cc: Uma Shankar < > uma.shankar@xxxxxxxxx > > > Signed-off-by: Anshuman Gupta < > anshuman.gupta@xxxxxxxxx > > > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c > index 21f39c94056e..389a0f2d3a14 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -4689,7 +4689,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, > int max_dc; > > if (INTEL_GEN(dev_priv) >= 12) { > - max_dc = 4; > + if (IS_DG1(dev_priv)) Better change to IS_DGFX() as DC6 is a SOC power-saving state, no discrete card will enter it. With this change: Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > + max_dc = 3; > + else > + max_dc = 4; > /* > * DC9 has a separate HW flow from the rest of the DC states, > * not depending on the DMC firmware. It's needed by system > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx