On Fri, Jul 24, 2020 at 02:39:02PM -0700, Lucas De Marchi wrote:
> From: Aditya Swarup <aditya.swarup@xxxxxxxxx>
>
> DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
> DPLL2 and DPLL3 drive DDIC/DDID.
Since this is a DG1-specific commit with DG1-specific macros, we should
also use the DG1-specific terminology in the commit message to avoid
confusion (i.e., DDI-TC1 and DDI-TC2 instead of DDIC/DDID).
Aside from that,
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
>
> Introduce DG1_DPLL_CFCRx() helper macros to configure
> DPLL registers.
>
> Bspec: 50288, 50299
>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Signed-off-by: Aditya Swarup <aditya.swarup@xxxxxxxxx>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 17 +++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++++++++++-
> 2 files changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> index 5d9a2bc371e7..205542fb8dc7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
> @@ -154,6 +154,23 @@ enum intel_dpll_id {
> * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
> */
> DPLL_ID_TGL_MGPLL6 = 8,
> +
> + /**
> + * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
> + */
> + DPLL_ID_DG1_DPLL0 = 0,
> + /**
> + * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
> + */
> + DPLL_ID_DG1_DPLL1 = 1,
> + /**
> + * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
> + */
> + DPLL_ID_DG1_DPLL2 = 2,
> + /**
> + * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
> + */
> + DPLL_ID_DG1_DPLL3 = 3,
> };
>
> #define I915_NUM_PLLS 9
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3767b32127da..986e31af7763 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -242,7 +242,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))
> #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
> -#define _MMIO_PLL3(pll, a, b, c) _MMIO(_PICK(pll, a, b, c))
> +#define _MMIO_PLL3(pll, ...) _MMIO(_PICK(pll, __VA_ARGS__))
> +
>
> /*
> * Device info offset array based helpers for groups of registers with unevenly
> @@ -10547,6 +10548,20 @@ enum skl_power_gate {
> #define RKL_DPLL_CFGCR1(pll) _MMIO_PLL(pll, _TGL_DPLL0_CFGCR1, \
> _TGL_DPLL1_CFGCR1)
>
> +#define _DG1_DPLL2_CFGCR0 0x16C284
> +#define _DG1_DPLL3_CFGCR0 0x16C28C
> +#define DG1_DPLL_CFGCR0(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
> + _TGL_DPLL1_CFGCR0, \
> + _DG1_DPLL2_CFGCR0, \
> + _DG1_DPLL3_CFGCR0)
> +
> +#define _DG1_DPLL2_CFGCR1 0x16C288
> +#define _DG1_DPLL3_CFGCR1 0x16C290
> +#define DG1_DPLL_CFGCR1(pll) _MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
> + _TGL_DPLL1_CFGCR1, \
> + _DG1_DPLL2_CFGCR1, \
> + _DG1_DPLL3_CFGCR1)
> +
> #define _DKL_PHY1_BASE 0x168000
> #define _DKL_PHY2_BASE 0x169000
> #define _DKL_PHY3_BASE 0x16A000
> --
> 2.26.2
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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