Whether this is an arbitrary stall or a vital ingredient, neverthess the impact is noticeable. If we do not have the stall around the xcs invalidation before a request, writes within that request sometimes go astray. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2169 Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 353b1717fe84..104bef04498d 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -4761,10 +4761,12 @@ static int gen12_emit_flush_render(struct i915_request *request, static int gen12_emit_flush(struct i915_request *request, u32 mode) { +#define WA_CNT 32 /* Magic delay */ intel_engine_mask_t aux_inv = 0; u32 cmd, *cs; + int n; - cmd = 4; + cmd = 4 * WA_CNT; if (mode & EMIT_INVALIDATE) cmd += 2; if (mode & EMIT_INVALIDATE) @@ -4781,7 +4783,8 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode) cmd = MI_FLUSH_DW + 1; - /* We always require a command barrier so that subsequent + /* + * We always require a command barrier so that subsequent * commands, such as breadcrumb interrupts, are strictly ordered * wrt the contents of the write cache being flushed to memory * (and thus being coherent from the CPU). @@ -4794,10 +4797,12 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode) cmd |= MI_INVALIDATE_BSD; } - *cs++ = cmd; - *cs++ = LRC_PPHWSP_SCRATCH_ADDR; - *cs++ = 0; /* upper addr */ - *cs++ = 0; /* value */ + for (n = 0; n < WA_CNT; n++) { + *cs++ = cmd; + *cs++ = LRC_PPHWSP_SCRATCH_ADDR; + *cs++ = 0; /* upper addr */ + *cs++ = 0; /* value */ + } if (aux_inv) { /* hsdes: 1809175790 */ struct intel_engine_cs *engine; @@ -4818,6 +4823,7 @@ static int gen12_emit_flush(struct i915_request *request, u32 mode) intel_ring_advance(request, cs); return 0; +#undef WA_CNT } static void assert_request_valid(struct i915_request *rq) -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
