+}
+
+static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
+{
+ /* OA buffer trigger report 2/6 used by performance query */
+ whitelist_reg(w, GEN12_OAG_OAREPORTTRIG2);
+ whitelist_reg(w, GEN12_OAG_OAREPORTTRIG6);
+}
+
static void gen9_whitelist_build(struct i915_wa_list *w)
{
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
@@ -1400,6 +1414,9 @@ static void gen9_whitelist_build(struct i915_wa_list *w)
/* WaSendPushConstantsFromMMIO:skl,bxt */
whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+ /* Performance counters support */
+ gen9_whitelist_build_performance_counters(w);
}
static void skl_whitelist_build(struct intel_engine_cs *engine)
@@ -1493,6 +1510,9 @@ static void cnl_whitelist_build(struct intel_engine_cs *engine)
/* WaEnablePreemptionGranularityControlByUMD:cnl */
whitelist_reg(w, GEN8_CS_CHICKEN1);
+
+ /* Performance counters support */
+ gen9_whitelist_build_performance_counters(w);
}
static void icl_whitelist_build(struct intel_engine_cs *engine)
@@ -1522,6 +1542,9 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
whitelist_reg_ext(w, PS_INVOCATION_COUNT,
RING_FORCE_TO_NONPRIV_ACCESS_RD |
RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ /* Performance counters support */
+ gen9_whitelist_build_performance_counters(w);
break;
case VIDEO_DECODE_CLASS:
@@ -1572,6 +1595,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine)
/* Wa_1806527549:tgl */
whitelist_reg(w, HIZ_CHICKEN);
+
+ /* Performance counters support */
+ gen12_whitelist_build_performance_counters(w);
break;
default:
whitelist_reg_ext(w,
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index febc9e6692ba..3b1d3dbcd477 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -934,6 +934,10 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
static const struct regmask pardon[] = {
{ GEN9_CTX_PREEMPT_REG, INTEL_GEN_MASK(9, 9) },
{ GEN8_L3SQCREG4, INTEL_GEN_MASK(9, 9) },
+ { OAREPORTTRIG2, INTEL_GEN_MASK(8, 11) },
+ { OAREPORTTRIG6, INTEL_GEN_MASK(8, 11) },
+ { GEN12_OAG_OAREPORTTRIG2, INTEL_GEN_MASK(12, 12) },
+ { GEN12_OAG_OAREPORTTRIG6, INTEL_GEN_MASK(12, 12) },