On Mon, 2020-07-20 at 10:09 -0700, José Roberto de Souza wrote: > This new HBR2 table for TGL-U and TGL-Y is required to pass > DisplayPort compliance. > > BSpec: 49291 > Cc: Khaled Almahallawy <khaled.almahallawy@xxxxxxxxx> > Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c > b/drivers/gpu/drm/i915/display/intel_ddi.c > index 714b2bc96f23..de5b216561d8 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -706,6 +706,20 @@ static const struct cnl_ddi_buf_trans > tgl_combo_phy_ddi_translations_dp_hbr2[] = > { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > }; > > +static const struct cnl_ddi_buf_trans > tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = { > + /* NT mV Trans mV > db */ > + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ > + { 0xA, 0x4F, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ > + { 0xC, 0x60, 0x32, 0x00, 0x0D }, /* 350 700 6.0 */ > + { 0xC, 0x7F, 0x2D, 0x00, 0x12 }, /* 350 900 8.2 */ > + { 0xC, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ > + { 0xC, 0x6F, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ > + { 0x6, 0x7D, 0x32, 0x00, 0x0D }, /* 500 900 5.1 */ > + { 0x6, 0x60, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ > + { 0x6, 0x7F, 0x34, 0x00, 0x0B }, /* 600 900 3.5 */ > + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ > +}; > + > /* > * Cloned the HOBL entry to comply with the voltage and pre-emphasis > entries > * that DisplayPort specification requires > @@ -1087,6 +1101,11 @@ tgl_get_combo_buf_trans(struct intel_encoder > *encoder, int type, int rate, > if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) { > return icl_get_combo_buf_trans(encoder, type, rate, > n_entries); > } else if (rate > 270000) { > + if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { > + *n_entries = > ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2); > + return > tgl_uy_combo_phy_ddi_translations_dp_hbr2; > + } > + > *n_entries = > ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); > return tgl_combo_phy_ddi_translations_dp_hbr2; > } Match bspecs Reviewed-by: Khaled Almahallawy<khaled.almahallawy@xxxxxxxxx> _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx