On 17/07/2020 04:57, Umesh Nerlige Ramappa wrote:
From: Piotr Maciejewski <piotr.maciejewski@xxxxxxxxx>
It is useful to have markers in the OA reports to identify triggered
reports. Whitelist some OA counters that can be used as markers.
A triggered report can be found faster if we can sample the HW tail and
head registers when the report was triggered. Whitelist OA buffer
specific registers.
Signed-off-by: Piotr Maciejewski <piotr.maciejewski@xxxxxxxxx>
Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@xxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 34 +++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++
2 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 582a2c8cd219..40a38023a05b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1370,6 +1370,23 @@ static void gen9_whitelist_build_performance_counters(struct i915_wa_list *w)
/* OA buffer trigger report 2/6 used by performance query */
whitelist_reg(w, OAREPORTTRIG2);
whitelist_reg(w, OAREPORTTRIG6);
+
+ /* Performance counters A18-20 used by tbs marker query */
+ whitelist_reg_ext(w, OA_PERF_COUNTER_A18,
+ RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ whitelist_reg(w, OA_PERF_COUNTER_A20);
+ whitelist_reg(w, OA_PERF_COUNTER_A20_UPPER);
+
+ /* Read access to gpu ticks */
+ whitelist_reg_ext(w, GEN8_GPU_TICKS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+ /* Read access to: oa status, head, tail, buffer settings */
+ whitelist_reg_ext(w, GEN8_OASTATUS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
@@ -1377,6 +1394,23 @@ static void gen12_whitelist_build_performance_counters(struct i915_wa_list *w)
/* OA buffer trigger report 2/6 used by performance query */
whitelist_reg(w, GEN12_OAG_OAREPORTTRIG2);
whitelist_reg(w, GEN12_OAG_OAREPORTTRIG6);
+
+ /* Performance counters A18-20 used by tbs marker query */
+ whitelist_reg_ext(w, GEN12_OAG_PERF_COUNTER_A18,
+ RING_FORCE_TO_NONPRIV_ACCESS_RW |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
+
+ whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A20);
+ whitelist_reg(w, GEN12_OAG_PERF_COUNTER_A20_UPPER);
+
+ /* Read access to gpu ticks */
+ whitelist_reg_ext(w, GEN12_OAG_GPU_TICKS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD);
+
+ /* Read access to: oa status, head, tail, buffer settings */
+ whitelist_reg_ext(w, GEN12_OAG_OASTATUS,
+ RING_FORCE_TO_NONPRIV_ACCESS_RD |
+ RING_FORCE_TO_NONPRIV_RANGE_4);
}
static void gen9_whitelist_build(struct i915_wa_list *w)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b9607ac3620d..33653aa0cfd3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -675,6 +675,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0
#define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */
+#define GEN8_GPU_TICKS _MMIO(0x2910)
#define GEN8_OASTATUS _MMIO(0x2b08)
#define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3)
#define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2)
@@ -731,6 +732,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2)
#define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1)
+#define GEN12_OAG_GPU_TICKS _MMIO(0xda90)
#define GEN12_OAG_OASTATUS _MMIO(0xdafc)
#define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2)
#define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1)
@@ -972,6 +974,19 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24
#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28
+/* Performance counters registers */
+#define OA_PERF_COUNTER_A18 _MMIO(0x2890)
+#define OA_PERF_COUNTER_A19 _MMIO(0x2898)
+#define OA_PERF_COUNTER_A20 _MMIO(0x28A0)
+#define OA_PERF_COUNTER_A20_UPPER _MMIO(0x28A4)
#define OA_PERF_COUNTER_A(idx) _MMIO(0x2800 + 8 * (idx))
+
+/* Gen12 Performance counters registers */
+#define GEN12_OAG_PERF_COUNTER_A16 _MMIO(0xDA00)
+#define GEN12_OAG_PERF_COUNTER_A18 _MMIO(0xDA10)
+#define GEN12_OAG_PERF_COUNTER_A19 _MMIO(0xDA18)
+#define GEN12_OAG_PERF_COUNTER_A20 _MMIO(0xDA20)
+#define GEN12_OAG_PERF_COUNTER_A20_UPPER _MMIO(0xDA24)
#define GEN12_OA_PERF_COUNTER_A(idx) _MMIO(0xD980 + 8 * (idx)
+
/* Same layout as OASTARTTRIGX */
#define GEN12_OAG_OASTARTTRIG1 _MMIO(0xd900)
#define GEN12_OAG_OASTARTTRIG2 _MMIO(0xd904)
I think this deserves its own i915-perf revision bump.
Thanks,
-Lionel
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