Quoting Ville Syrjala (2020-07-14 19:51:28)
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Since g4x the CFB base only takes a 28bit offset into stolen.
> Not sure if the CFB is allowed to start below that limit but
> then extend beyond it. Let's assume not and just restrict the
> allocation to the first 256MiB (in the unlikely case
> we have more stolen than that).
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 85723fba6002..448e966bad11 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -424,6 +424,14 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
> fbc->no_fbc_reason = reason;
> }
>
> +static u64 intel_fbc_cfb_base_max(struct drm_i915_private *i915)
> +{
> + if (INTEL_GEN(i915) >= 5 || IS_G4X(i915))
> + return BIT(28);
> + else
> + return BIT(32);
BIT_ULL(32)
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