On Tue, Jul 14, 2020 at 06:31:41PM +0300, Imre Deak wrote:
> The driver enables the DDI function in the DDI_BUF_CTL register before
> starting the link training and disables it when disabling the output. It
> also gets disabled/re-enabled during link re-trainining.
>
> Except of the above the value we program to the register (intel_dp->DP)
> doesn't change, so no need to reprogram the register when changing the
> link training patterns.
>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
The only concern I had was the buf trans stuff for hsw/bdw/skl,
but looks like hsw_set_signal_levels() does everything we need.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 4 ----
> 1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c467f18d5e1b..424d59671561 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4060,7 +4060,6 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
> - enum port port = dp_to_dig_port(intel_dp)->base.port;
> u32 temp;
>
> temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
> @@ -4085,9 +4084,6 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
> }
>
> intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
> -
> - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> - intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> }
>
> static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
> --
> 2.23.1
>
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--
Ville Syrjälä
Intel
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