On Wed, Jul 08, 2020 at 02:29:47PM -0700, José Roberto de Souza wrote:
> As today those 2 WAs have different implementation between TGL and DG1
> WA pages but checking the HSD it is clear that DG1 implementation
> should be used for both,
I couldn't really find any conclusions in any of the hsds to say that
disabling the TE DOP clock gating is sufficient to deal with the other
issues. However the dg1 w/a page does say that, so I guess it's good
enough.
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> also to do so is easier as we just need to
> extend WA 1407928979 to B* stepping.
>
> Both WAs are need to fix some possible render corruptions.
>
> DG1 initial patches were not merged yet, as soon it is this WAs should
> be applied to DG1 as well.
>
> BSpec: 53508
> BSpec: 52890
> Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 ++++++++-----
> 1 file changed, 8 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 2da366821dda..3d31b763d9c9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1649,11 +1649,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> GEN7_SARCHKMD,
> GEN7_DISABLE_SAMPLER_PREFETCH);
>
> - /* Wa_1407928979:tgl */
> - wa_write_or(wal,
> - GEN7_FF_THREAD_MODE,
> - GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
> -
> /* Wa_1408615072:tgl */
> wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
> VSUNIT_CLKGATE_DIS_TGL);
> @@ -1677,6 +1672,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> * Wa_14010229206:tgl
> */
> wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
> +
> + /*
> + * Wa_1407928979:tgl A*
> + * Wa_18011464164:tgl B0+
> + * Wa_22010931296:tgl B0+
> + */
> + wa_write_or(wal, GEN7_FF_THREAD_MODE,
> + GEN12_FF_TESSELATION_DOP_GATE_DISABLE);
> }
>
> if (IS_GEN(i915, 11)) {
> --
> 2.27.0
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
