On Tue, 2020-06-16 at 20:30 -0700, Matt Roper wrote:
> RKL uses a slightly different bit layout for the DPCLKA_CFGCR0 register.
>
> v2:
> - Fix inverted mask application when updating ICL_DPCLKA_CFGCR0
> - Checkpatch style fixes
>
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Bspec: 50287
> Cc: Aditya Swarup <aditya.swarup@xxxxxxxxx>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 18 +++++++++++++++---
> drivers/gpu/drm/i915/display/intel_display.c | 15 ++++++++++++---
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> 3 files changed, 33 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ca7bb2294d2b..8790f221dc77 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2770,7 +2770,9 @@ hsw_set_signal_levels(struct intel_dp *intel_dp)
> static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> enum phy phy)
> {
> - if (intel_phy_is_combo(dev_priv, phy)) {
> + if (IS_ROCKETLAKE(dev_priv)) {
> + return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + } else if (intel_phy_is_combo(dev_priv, phy)) {
> return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> } else if (intel_phy_is_tc(dev_priv, phy)) {
> enum tc_port tc_port = intel_port_to_tc(dev_priv,
> @@ -2797,6 +2799,16 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
>
> if (intel_phy_is_combo(dev_priv, phy)) {
> + u32 mask, sel;
> +
> + if (IS_ROCKETLAKE(dev_priv)) {
> + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> + } else {
> + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> + }
> +
> /*
> * Even though this register references DDIs, note that we
> * want to pass the PHY rather than the port (DDI). For
> @@ -2807,8 +2819,8 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder,
> * Clock Select chooses the PLL for both DDIA and DDID and
> * drives port A in all cases."
> */
> - val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> - val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> + val &= ~mask;
> + val |= sel;
> intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7457813ef273..6c2bb3354b86 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10785,9 +10785,18 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port,
> u32 temp;
>
> if (intel_phy_is_combo(dev_priv, phy)) {
> - temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) &
> - ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> - id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> + u32 mask, shift;
> +
> + if (IS_ROCKETLAKE(dev_priv)) {
> + mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> + } else {
> + mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> + }
> +
> + temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & mask;
> + id = temp >> shift;
> port_dpll_id = ICL_PORT_DPLL_DEFAULT;
> } else if (intel_phy_is_tc(dev_priv, phy)) {
> u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f09120cac89a..45bda5819abd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10195,12 +10195,18 @@ enum skl_power_gate {
>
> #define ICL_DPCLKA_CFGCR0 _MMIO(0x164280)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10, 11, 24))
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) REG_BIT((phy) + 10)
> #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \
> (tc_port) + 12 : \
> (tc_port) - PORT_TC4 + 21))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) * 2)
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> #define ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) << ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) _PICK(phy, 0, 2, 4, 27)
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) \
> + (3 << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) \
> + ((pll) << RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>
> /* CNL PLL */
> #define DPLL0_ENABLE 0x46010
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