On Thu, Jul 02, 2020 at 09:24:49PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Stop using HBR2/3 support as a proxy for TPS3/4 support.
> The two are no longer 1:1 in the hardware, arguably they
> never were due to HSW ULX which does support TPS3 while
> being limited to HBR1.
>
> In more recent times GLK gained support for TPS4 while
> being limited to HBR2. And on CNL+ some ports support
> HBR3 while others are limited to HBR2, but all ports
> support TPS4.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Makes sense to me
Reviewed-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 12 +++-----
> drivers/gpu/drm/i915/display/intel_dp.h | 4 +--
> .../drm/i915/display/intel_dp_link_training.c | 29 +++++++------------
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> 4 files changed, 17 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c9b93c5706af..5ac182357fc9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1799,18 +1799,14 @@ intel_dp_aux_init(struct intel_dp *intel_dp)
> intel_dp->aux.transfer = intel_dp_aux_transfer;
> }
>
> -bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
> +bool intel_dp_source_supports_tps3(struct drm_i915_private *i915)
> {
> - int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
> -
> - return max_rate >= 540000;
> + return INTEL_GEN(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);
> }
>
> -bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
> +bool intel_dp_source_supports_tps4(struct drm_i915_private *i915)
> {
> - int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
> -
> - return max_rate >= 810000;
> + return INTEL_GEN(i915) >= 10 || IS_GEMINILAKE(i915);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 0a8950f744f6..d597a9848397 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -94,8 +94,8 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp);
> void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
> void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
> u8 *link_bw, u8 *rate_select);
> -bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
> -bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
> +bool intel_dp_source_supports_tps3(struct drm_i915_private *i915);
> +bool intel_dp_source_supports_tps4(struct drm_i915_private *i915);
> bool
> intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 2493142a70e9..57c2089c9f5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -259,41 +259,32 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
> */
> static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
> {
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> bool source_tps3, sink_tps3, source_tps4, sink_tps4;
>
> - /*
> - * Intel platforms that support HBR3 also support TPS4. It is mandatory
> - * for all downstream devices that support HBR3. There are no known eDP
> - * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
> - * specification.
> - */
> - source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
> + source_tps4 = intel_dp_source_supports_tps4(i915);
> sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
> if (source_tps4 && sink_tps4) {
> return DP_TRAINING_PATTERN_4;
> } else if (intel_dp->link_rate == 810000) {
> if (!source_tps4)
> - drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - "8.1 Gbps link rate without source HBR3/TPS4 support\n");
> + drm_dbg_kms(&i915->drm,
> + "8.1 Gbps link rate without source TPS4 support\n");
> if (!sink_tps4)
> - drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> + drm_dbg_kms(&i915->drm,
> "8.1 Gbps link rate without sink TPS4 support\n");
> }
> - /*
> - * Intel platforms that support HBR2 also support TPS3. TPS3 support is
> - * also mandatory for downstream devices that support HBR2. However, not
> - * all sinks follow the spec.
> - */
> - source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
> +
> + source_tps3 = intel_dp_source_supports_tps3(i915);
> sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
> if (source_tps3 && sink_tps3) {
> return DP_TRAINING_PATTERN_3;
> } else if (intel_dp->link_rate >= 540000) {
> if (!source_tps3)
> - drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> - ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
> + drm_dbg_kms(&i915->drm,
> + ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
> if (!sink_tps3)
> - drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
> + drm_dbg_kms(&i915->drm,
> ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 611cb8d74811..5ba1aa2c6748 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -451,7 +451,7 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
> val |= EDP_PSR_TP2_TP3_TIME_2500us;
>
> check_tp3_sel:
> - if (intel_dp_source_supports_hbr2(intel_dp) &&
> + if (intel_dp_source_supports_tps3(dev_priv) &&
> drm_dp_tps3_supported(intel_dp->dpcd))
> val |= EDP_PSR_TP1_TP3_SEL;
> else
> --
> 2.26.2
>
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