On Wed, Jun 24, 2020 at 02:57:23PM -0700, Matt Atwood wrote:
Set the title to drm/i915/gen12: Impl... and let go the semicolon.
> Update code to reflect recent bspec changes
>
> Bspec: 52890
> Bspec: 53508
>
> Signed-off-by: Matt Atwood <matthew.s.atwood@xxxxxxxxx>
With the title fixed,
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c3eeebadc0b8..22395be35364 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -6007,6 +6007,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> struct i915_power_well *well;
> + u32 val;
>
> gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>
> @@ -6043,6 +6044,13 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
>
> if (resume && dev_priv->csr.dmc_payload)
> intel_csr_load_program(dev_priv);
> +
> + /* Wa_14011508470 */
> + if (IS_GEN(dev_priv, 12)) {
> + val = DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM |
> + DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
> + intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
> + }
> }
>
> static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 450564e28332..5344d20c9070 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8105,6 +8105,12 @@ enum hardware_error {
> #define MASK_WAKEMEM (1 << 13)
> #define CNL_DDI_CLOCK_REG_ACCESS_ON (1 << 7)
>
> +#define GEN11_CHICKEN_DCPR_2 _MMIO(0x46434)
> +#define DCPR_MASK_MAXLATENCY_MEMUP_CLR REG_BIT(27)
> +#define DCPR_MASK_LPMODE REG_BIT(26)
> +#define DCPR_SEND_RESP_IMM REG_BIT(25)
> +#define DCPR_CLEAR_MEMSTAT_DIS REG_BIT(24)
> +
> #define SKL_DFSM _MMIO(0x51000)
> #define SKL_DFSM_DISPLAY_PM_DISABLE (1 << 27)
> #define SKL_DFSM_DISPLAY_HDCP_DISABLE (1 << 25)
> --
> 2.21.3
>
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