On Wed, 2020-04-29 at 13:10 +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Parametrize the FBC_CONTROL bits for neater code. > > Also add the one missing bit: "stop compression on modification". > Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_fbc.c | 8 ++++---- > drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++++------- > 2 files changed, 15 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c > index 56eeafa645de..dbef58af4b94 100644 > --- a/drivers/gpu/drm/i915/display/intel_fbc.c > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c > @@ -133,13 +133,13 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) > > /* enable it... */ > fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL); > - fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; > + fbc_ctl &= FBC_CTL_INTERVAL(0x3fff); > fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; > if (IS_I945GM(dev_priv)) > fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ > - fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; > + fbc_ctl |= FBC_CTL_STRIDE(cfb_pitch & 0xff); > if (params->fence_id >= 0) > - fbc_ctl |= params->fence_id; > + fbc_ctl |= FBC_CTL_FENCENO(params->fence_id); > intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); > } > > @@ -1452,7 +1452,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) > /* This value was pulled out of someone's hat */ > if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) > intel_de_write(dev_priv, FBC_CONTROL, > - 500 << FBC_CTL_INTERVAL_SHIFT); > + FBC_CTL_INTERVAL(500)); > > /* We still don't have any sort of hardware state readout for FBC, so > * deactivate it in case the BIOS activated it to make sure software > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 088215025661..e9fb64e8f28f 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3194,13 +3194,17 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ > #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ > #define FBC_CONTROL _MMIO(0x3208) > -#define FBC_CTL_EN (1 << 31) > -#define FBC_CTL_PERIODIC (1 << 30) > -#define FBC_CTL_INTERVAL_SHIFT (16) > -#define FBC_CTL_UNCOMPRESSIBLE (1 << 14) > -#define FBC_CTL_C3_IDLE (1 << 13) > -#define FBC_CTL_STRIDE_SHIFT (5) > -#define FBC_CTL_FENCENO_SHIFT (0) > +#define FBC_CTL_EN REG_BIT(31) > +#define FBC_CTL_PERIODIC REG_BIT(30) > +#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) > +#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) > +#define FBC_CTL_STOP_ON_MOD REG_BIT(15) > +#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ > +#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm */ > +#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) > +#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) > +#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) > +#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) > #define FBC_COMMAND _MMIO(0x320c) > #define FBC_CMD_COMPRESS (1 << 0) > #define FBC_STATUS _MMIO(0x3210) _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
