Am 2020-06-23 um 3:39 a.m. schrieb Daniel Vetter: > On Fri, Jun 12, 2020 at 1:35 AM Felix Kuehling <felix.kuehling@xxxxxxx> wrote: >> Am 2020-06-11 um 10:15 a.m. schrieb Jason Gunthorpe: >>> On Thu, Jun 11, 2020 at 10:34:30AM +0200, Daniel Vetter wrote: >>>>> I still have my doubts about allowing fence waiting from within shrinkers. >>>>> IMO ideally they should use a trywait approach, in order to allow memory >>>>> allocation during command submission for drivers that >>>>> publish fences before command submission. (Since early reservation object >>>>> release requires that). >>>> Yeah it is a bit annoying, e.g. for drm/scheduler I think we'll end up >>>> with a mempool to make sure it can handle it's allocations. >>>> >>>>> But since drivers are already waiting from within shrinkers and I take your >>>>> word for HMM requiring this, >>>> Yeah the big trouble is HMM and mmu notifiers. That's the really awkward >>>> one, the shrinker one is a lot less established. >>> I really question if HW that needs something like DMA fence should >>> even be using mmu notifiers - the best use is HW that can fence the >>> DMA directly without having to get involved with some command stream >>> processing. >>> >>> Or at the very least it should not be a generic DMA fence but a >>> narrowed completion tied only into the same GPU driver's command >>> completion processing which should be able to progress without >>> blocking. >>> >>> The intent of notifiers was never to endlessly block while vast >>> amounts of SW does work. >>> >>> Going around and switching everything in a GPU to GFP_ATOMIC seems >>> like bad idea. >>> >>>> I've pinged a bunch of armsoc gpu driver people and ask them how much this >>>> hurts, so that we have a clear answer. On x86 I don't think we have much >>>> of a choice on this, with userptr in amd and i915 and hmm work in nouveau >>>> (but nouveau I think doesn't use dma_fence in there). >> Soon nouveau will get company. We're working on a recoverable page fault >> implementation for HMM in amdgpu where we'll need to update page tables >> using the GPUs SDMA engine and wait for corresponding fences in MMU >> notifiers. > Can you pls cc these patches to dri-devel when they show up? Depending > upon how your hw works there's and endless amount of bad things that > can happen. Yes, I'll do that. > > Also I think (again depending upon how the hw exactly works) this > stuff would be a perfect example for the dma_fence annotations. We have already applied your patch series to our development branch. I haven't looked into what annotations we'd have to add to our new code yet. > > The worst case is if your hw cannot preempt while a hw page fault is > pending. That means none of the dma_fence will ever signal (the amdkfd > preempt ctx fences wont, and the classic fences from amdgpu might be > also stall). At least when you're unlucky and the fence you're waiting > on somehow (anywhere in its dependency chain really) need the engine > that's currently blocked waiting for the hw page fault. Our HW can preempt while handling a page fault, at least on the GPU generation we're working on now. On other GPUs we haven't included in our initial effort, we will not be able to preempt while a page fault is in progress. This is problematic, but that's for reasons related to our GPU hardware scheduler and unrelated to fences. > > That in turn means anything you do in your hw page fault handler is in > the critical section for dma fence signalling, which has far reaching > implications. I'm not sure I agree, at least for KFD. The only place where KFD uses fences that depend on preemptions is eviction fences. And we can get rid of those if we can preempt GPU access to specific BOs by invalidating GPU PTEs. That way we don't need to preempt the GPU queues while a page fault is in progress. Instead we would create more page faults. That assumes that we can invalidate GPU PTEs without depending on fences. We've discussed possible deadlocks due to memory allocations needed on that code paths for IBs or page tables. We've already eliminated page table allocations and reservation locks on the PTE invalidation code path. And we're using a separate scheduler entity so we can't get stuck behind other IBs that depend on fences. IIRC, Christian also implemented a separate memory pool for IBs for this code path. Regards, Felix > -Daniel > >> Regards, >> Felix >> >> >>> Right, nor will RDMA ODP. >>> >>> Jason >>> _______________________________________________ >>> amd-gfx mailing list >>> amd-gfx@xxxxxxxxxxxxxxxxxxxxx >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> _______________________________________________ >> dri-devel mailing list >> dri-devel@xxxxxxxxxxxxxxxxxxxxx >> https://lists.freedesktop.org/mailman/listinfo/dri-devel > > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
