On Tue, 2020-06-23 at 11:24 +0300, Imre Deak wrote:
> The spec requires enabling the MST Virtual Channel payload allocation
> - in a seperate step - after the transcoder is enabled, follow this.
>
Is the next step but indeed a different step.
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 8 +++-----
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 8 ++++++++
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 73d6cc29291a..884b507c5f55 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1653,7 +1653,6 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> - u32 ctl;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> enum transcoder master_transcoder = crtc_state->master_transcoder;
> @@ -1671,10 +1670,9 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
> TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
> }
>
> - ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
> - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
> - ctl |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
> + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
> + intel_ddi_transcoder_func_reg_val_get(encoder,
> + crtc_state));
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 0c891bdd1aa0..3426ce8bbbd0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -539,6 +539,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
> struct intel_digital_port *intel_dig_port = intel_mst->primary;
> struct intel_dp *intel_dp = &intel_dig_port->dp;
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + u32 val;
>
> drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
>
> @@ -546,6 +547,13 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
>
> intel_ddi_enable_transcoder_func(encoder, pipe_config);
>
> + val = intel_de_read(dev_priv,
> + TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
> + val |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
> + intel_de_write(dev_priv,
> + TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder),
> + val);
> +
> drm_dbg_kms(&dev_priv->drm, "active links %d\n",
> intel_dp->active_mst_links);
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
