Quoting Chris Wilson (2020-06-11 09:01:36) > +static void > +ivb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) > + /* > + * BSpec recommends 8x4 when MSAA is used, > + * however in practice 16x4 seems fastest. > + * > + * Note that PS/WM thread counts depend on the WIZ hashing > + * disable bit, which we don't touch here, but it's good > + * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). > + */ > + wa_add(wal, GEN7_GT_MODE, 0, > + _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4), > + GEN6_WIZ_HASHING_16x4); Fwiw, from gen8+, we have this in the ctx workarounds. Not sure if that's a better spot or not. An inquiry for later, as it is passing the tests for now :) -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
