Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
> Rescue the GT workarounds from being buried inside init_clock_gating so
> that we remember to apply them after a GT reset, and that they are
> included in our verification that the workarounds are applied.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 14 ++++++++++++++
> drivers/gpu/drm/i915/intel_pm.c | 10 ----------
> 2 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 7b4f3434eb6b..f8b9e104378e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -714,6 +714,18 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
> return 0;
> }
>
> +static void
> +ilk_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> + wa_masked_en(wal,_3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED);
> +
> + /* WaDisableRenderCachePipelinedFlush:ilk */
> + wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
> +
> + /* WaDisable_RenderCache_OperationalFlush:ilk */
> + wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
> +}
> +
> static void
> snb_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> {
> @@ -1195,6 +1207,8 @@ gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
> ivb_gt_workarounds_init(i915, wal);
> else if (IS_GEN(i915, 6))
> snb_gt_workarounds_init(i915, wal);
> + else if (IS_GEN(i915, 5))
> + ilk_gt_workarounds_init(i915, wal);
> else if (INTEL_GEN(i915) <= 8)
> return;
> else
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b4bea6451418..7d82a7144a13 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6921,16 +6921,6 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
> I915_READ(ILK_DISPLAY_CHICKEN2) |
> ILK_ELPIN_409_SELECT);
> - I915_WRITE(_3D_CHICKEN2,
> - _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
> - _3D_CHICKEN2_WM_READ_PIPELINED);
> -
> - /* WaDisableRenderCachePipelinedFlush:ilk */
> - I915_WRITE(CACHE_MODE_0,
> - _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
> -
> - /* WaDisable_RenderCache_OperationalFlush:ilk */
> - I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
>
> g4x_disable_trickle_feed(dev_priv);
>
> --
> 2.20.1
>
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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