On Fri, Jan 25, 2013 at 04:59:11PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni at intel.com> > > The current code was wrong in many different ways, so this is a full > rewrite. We don't have "different power wells for different parts of > the GPU", we have a single power well, but we have multiple registers > that can be used to request enabling/disabling the power well. So > let's be a good citizen and only use the register we're suppose to > use, except when we're loading the driver, where we clear the request > made by the BIOS. > > If any of the registers is requesting the power well to be enabled, it > will be enabled. If none of the registers is requesting the power well > to be enabled, it will be disabled. > > For now we're just forcing the power well to be enabled, but in the > next commits we'll change this. > > V2: > - Remove debug messages that could be misleading due to possible > race conditions with KVMr, Debug and BIOS. > - Don't wait on disabling: after a conversaion with a hardware > engineer we discovered that the "restriction" on bit 31 is just > for the "enable" case, and we don't even need to wait on the > "disable" case. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
