[PATCH 1/7] drm/i915: don't send DP idle pattern before normal pattern on HSW

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On Fri, Jan 25, 2013 at 04:59:10PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> 
> Previously I sent "drm/i915: don't read DP_TP_STATUS(PORT_A)", but
> after some more discussion I was told by a hardware engineer that we
> don't really need to send the idle patterns before the normal pattern
> in our current code: we only need this for a DP mode that we currently
> don't support. So for now, just kill the whole code. I've already
> asked for an update on the documentation, so at some point this code
> should match the docs.
> 
> This solves "Timed out waiting for DP idle patterns" and "unclaimed
> register" messages on eDP.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

Since we already have the code, and it should be harmless to run this on
DP ports B-D, can't we just disable this on port A? I fear that if we ever
get around to enable that funky other DP mode, we'll miss this and suffer
through some ugly bugs ...
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_dp.c |    9 ---------
>  1 file changed, 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 51fd797..f2fa219 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1785,16 +1785,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
>  		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
>  		case DP_TRAINING_PATTERN_DISABLE:
> -			temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
> -			I915_WRITE(DP_TP_CTL(port), temp);
> -
> -			if (wait_for((I915_READ(DP_TP_STATUS(port)) &
> -				      DP_TP_STATUS_IDLE_DONE), 1))
> -				DRM_ERROR("Timed out waiting for DP idle patterns\n");
> -
> -			temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
>  			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
> -
>  			break;
>  		case DP_TRAINING_PATTERN_1:
>  			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch


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