On Tue, 2020-05-12 at 20:41 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> According to the DP spec supporting vswing 1 + preemph 2 is
> mandatory. We don't have the hw settings for that though. In
> order to pretend to follow the DP spec let's just select
> vswing 0 + preemph 2 in this case (the DP spec says to use
> the requested preemph in preference to the vswing when the
> requested values aren't supported).
>
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 13 +------------
> 1 file changed, 1 insertion(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0924e041e1bf..4952918d0904 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3960,8 +3960,6 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
> (HAS_PCH_SPLIT(dev_priv) && port != PORT_A))
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
> - else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
> - return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> else
> return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
> }
> @@ -3988,16 +3986,6 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing)
> default:
> return DP_TRAIN_PRE_EMPH_LEVEL_0;
> }
> - } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
> - switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> - return DP_TRAIN_PRE_EMPH_LEVEL_2;
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
> - case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
> - return DP_TRAIN_PRE_EMPH_LEVEL_1;
> - default:
> - return DP_TRAIN_PRE_EMPH_LEVEL_0;
> - }
> } else {
> switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
> @@ -4293,6 +4281,7 @@ static u32 ivb_cpu_edp_signal_levels(u8 train_set)
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
> return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
> + case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
> return EDP_LINK_TRAIN_400MV_6DB_IVB;
>
> case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
