We've tried this on EHL and it doesn't work.
The intent of the workaround is that the bit must be toggled after all south display registers are
accessed before entering a S0ix state. If any south display register is accessed after this bit is
toggled, it resets things and the bit needs to be toggled again.
When we test this on EHL, the workaround isn't working. Based on some additional testing
It appears that something is accessing a south display register after this point. We need to
find the correct location such that this is the last thing that accesses a south display register.
I suspect that this is also not working for ICL
Bob
--
Bob Paauwe
Bob.J.Paauwe@xxxxxxxxx
IOTG / Platform Software Engineering
Intel Corp. Folsom, CA
(916) 356-6193
(530) 409-0831 (cell)
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Swathi
> Dhanavanthri
> Sent: Wednesday, May 20, 2020 11:45 PM
> To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> Subject: [PATCH v3] drm/i915/ehl: Extend w/a 14010685332 to
> JSP/MCC
>
> This is a permanent w/a for JSL/EHL.This is to be applied to the
> PCH types on JSL/EHL ie JSP/MCC
> Bspec: 52888
>
> v2: Fixed the wrong usage of logical OR(ville)
> v3: Removed extra braces, changed the check(jose)
>
> Signed-off-by: Swathi Dhanavanthri <swathi.dhanavanthri@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index 4dc601dffc08..bc82d0d8ad5b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2902,8 +2902,10 @@ static void gen11_display_irq_reset(struct
> drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:icl */
> - if (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) {
> + /* Wa_14010685332:icl,jsl,ehl */
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_ICP ||
> + INTEL_PCH_TYPE(dev_priv) == PCH_JSP ||
> + INTEL_PCH_TYPE(dev_priv) == PCH_MCC) {
> intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> SBCLK_RUN_REFCLK_DIS,
> SBCLK_RUN_REFCLK_DIS);
> intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> --
> 2.20.1
>
> _______________________________________________
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
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