On Mon, May 18, 2020 at 12:41 PM Ramalingam C <ramalingam.c@xxxxxxxxx> wrote: > > On 2020-05-18 at 10:32:09 -0400, Sean Paul wrote: > > On Fri, May 15, 2020 at 10:48 AM Ramalingam C <ramalingam.c@xxxxxxxxx> wrote: > > > > > > On 2020-04-29 at 15:54:46 -0400, Sean Paul wrote: > > > > From: Sean Paul <seanpaul@xxxxxxxxxxxx> > > > > > > > > Changes in v6: > > > > -Rebased on -tip > > > > -Disabled HDCP over MST on GEN12 > > > > -Addressed Lyude's review comments in the QUERY_STREAM_ENCRYPTION_STATUS patch > > > > > > Sean, > > > > > > What is the test setup you have used? > > > > > > > Hi Ram, > > Thanks for the feedback. To be completely honest it's really > > frustrating that I'm just now getting questions and review feedback > > (which I've been begging for on IRC) on this review that could have > > been addressed ~5 months ago. It's super disruptive to have to keep > > switching back to this after a long hiatus and many i915 refactors > > complicating my rebases. > Hi Sean, > > As a developer I really feel bad for the delay happened in review. > I couldn't spend required time for understanding MST part hence I > couldn't review. > > Just for this series now I have started preparing myself on these topics, > hence started reviewing the series. > > If you are still interested to work on this, I can commit for regular reviews. > Thanks Ram. I'm still incentivized to get this in. Once you have had a chance to look over the whole series, I'll revise again. Sean > Thanks, > Ram. > > > > If no one wants this patchset, that's fine, please just let me know so > > I don't waste any more time. If Intel is interested, could we please > > stop the review trickle and lay out exactly what needs to be done to > > get this landed? > > > > Sean > > > > > > > I am afraid our CI dont have the coverage for MST capability yet to provide > > > the functional status of the code. > > > > > > -Ram. > > > > > > > > Sean Paul (16): > > > > drm/i915: Fix sha_text population code > > > > drm/i915: Clear the repeater bit on HDCP disable > > > > drm/i915: WARN if HDCP signalling is enabled upon disable > > > > drm/i915: Intercept Aksv writes in the aux hooks > > > > drm/i915: Use the cpu_transcoder in intel_hdcp to toggle HDCP > > > > signalling > > > > drm/i915: Factor out hdcp->value assignments > > > > drm/i915: Protect workers against disappearing connectors > > > > drm/i915: Don't fully disable HDCP on a port if multiple pipes are > > > > using it > > > > drm/i915: Support DP MST in enc_to_dig_port() function > > > > drm/i915: Use ddi_update_pipe in intel_dp_mst > > > > drm/i915: Factor out HDCP shim functions from dp for use by dp_mst > > > > drm/i915: Plumb port through hdcp init > > > > drm/i915: Add connector to hdcp_shim->check_link() > > > > drm/mst: Add support for QUERY_STREAM_ENCRYPTION_STATUS MST sideband > > > > message > > > > drm/i915: Print HDCP version info for all connectors > > > > drm/i915: Add HDCP 1.4 support for MST connectors > > > > > > > > drivers/gpu/drm/drm_dp_mst_topology.c | 142 ++++ > > > > drivers/gpu/drm/i915/Makefile | 1 + > > > > drivers/gpu/drm/i915/display/intel_ddi.c | 29 +- > > > > drivers/gpu/drm/i915/display/intel_ddi.h | 2 + > > > > .../drm/i915/display/intel_display_debugfs.c | 21 +- > > > > .../drm/i915/display/intel_display_types.h | 30 +- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 654 +-------------- > > > > drivers/gpu/drm/i915/display/intel_dp.h | 9 + > > > > drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 743 ++++++++++++++++++ > > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 19 + > > > > drivers/gpu/drm/i915/display/intel_hdcp.c | 217 +++-- > > > > drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +- > > > > drivers/gpu/drm/i915/display/intel_hdmi.c | 25 +- > > > > .../drm/selftests/test-drm_dp_mst_helper.c | 17 + > > > > include/drm/drm_dp_helper.h | 3 + > > > > include/drm/drm_dp_mst_helper.h | 44 ++ > > > > include/drm/drm_hdcp.h | 3 + > > > > 17 files changed, 1235 insertions(+), 726 deletions(-) > > > > create mode 100644 drivers/gpu/drm/i915/display/intel_dp_hdcp.c > > > > > > > > -- > > > > Sean Paul, Software Engineer, Google / Chromium OS > > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
