On Sat, May 16, 2020 at 02:31:02PM +0100, Chris Wilson wrote: > Count the number of CS_TIMESTAMP ticks and check that it matches our > expectations. Looks ok for everything except g4x/ilk. Those would need something like https://patchwork.freedesktop.org/patch/355944/?series=74145&rev=1 + read TIMESTAMP_UDW instead of TIMESTAMP. bw/cl still needs https://patchwork.freedesktop.org/patch/355946/?series=74145&rev=1 though the test seems a bit flaky on my cl. Sometimes the cycle count comes up short. Never seen it exceed the expected value, but it can come up significantly short. And curiously it does seem to have a tendency to come out as roughly some nice fraction (seen at least 1/2 and 1/4 quite a few times). Dunno if the tick rate actually changes due to some unknown circumstances, or if the counter just updates somehow lazily. Certainly polling the counter over a longer period does show it to tick at the expected rate. Anyways, test looks sane to me Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 113 +++++++++++++++++++++++ > 1 file changed, 113 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > index 242181a5214c..cac4cf2a5e1d 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > +++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c > @@ -5,10 +5,122 @@ > * Copyright © 2019 Intel Corporation > */ > > +#include <linux/sort.h> > + > +#include "intel_gt_clock_utils.h" > + > #include "selftest_llc.h" > #include "selftest_rc6.h" > #include "selftest_rps.h" > > +static int cmp_u64(const void *A, const void *B) > +{ > + const u64 *a = A, *b = B; > + > + if (a < b) > + return -1; > + else if (a > b) > + return 1; > + else > + return 0; > +} > + > +static int cmp_u32(const void *A, const void *B) > +{ > + const u32 *a = A, *b = B; > + > + if (a < b) > + return -1; > + else if (a > b) > + return 1; > + else > + return 0; > +} > + > +static void measure_clocks(struct intel_engine_cs *engine, > + u32 *out_cycles, ktime_t *out_dt) > +{ > + ktime_t dt[5]; > + u32 cycles[5]; > + int i; > + > + for (i = 0; i < 5; i++) { > + preempt_disable(); > + dt[i] = ktime_get(); > + cycles[i] = -ENGINE_READ_FW(engine, RING_TIMESTAMP); > + > + udelay(1000); > + > + dt[i] = ktime_sub(ktime_get(), dt[i]); > + cycles[i] += ENGINE_READ_FW(engine, RING_TIMESTAMP); > + preempt_enable(); > + } > + > + /* Use the median of both cycle/dt; close enough */ > + sort(cycles, 5, sizeof(*cycles), cmp_u32, NULL); > + *out_cycles = (cycles[1] + 2 * cycles[2] + cycles[3]) / 4; > + > + sort(dt, 5, sizeof(*dt), cmp_u64, NULL); > + *out_dt = div_u64(dt[1] + 2 * dt[2] + dt[3], 4); > +} > + > +static int live_gt_clocks(void *arg) > +{ > + struct intel_gt *gt = arg; > + struct intel_engine_cs *engine; > + enum intel_engine_id id; > + int err = 0; > + > + if (!RUNTIME_INFO(gt->i915)->cs_timestamp_frequency_hz) { /* unknown */ > + pr_info("CS_TIMESTAMP frequency unknown\n"); > + return 0; > + } > + > + if (INTEL_GEN(gt->i915) < 4) /* Any CS_TIMESTAMP? */ > + return 0; > + > + intel_gt_pm_get(gt); > + intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL); > + > + for_each_engine(engine, gt, id) { > + u32 cycles; > + u32 expected; > + u64 time; > + u64 dt; > + > + if (INTEL_GEN(engine->i915) < 7 && engine->id != RCS0) > + continue; > + > + measure_clocks(engine, &cycles, &dt); > + > + time = i915_cs_timestamp_ticks_to_ns(engine->i915, cycles); > + expected = i915_cs_timestamp_ns_to_ticks(engine->i915, dt); > + > + pr_info("%s: TIMESTAMP %d cycles [%lldns] in %lldns [%d cycles], using CS clock frequency of %uKHz\n", > + engine->name, cycles, time, dt, expected, > + RUNTIME_INFO(engine->i915)->cs_timestamp_frequency_hz / 1000); > + > + if (9 * time < 8 * dt || 8 * time > 9 * dt) { > + pr_err("%s: CS ticks did not match walltime!\n", > + engine->name); > + err = -EINVAL; > + break; > + } > + > + if (9 * expected < 8 * cycles || 8 * expected > 9 * cycles) { > + pr_err("%s: walltime did not match CS ticks!\n", > + engine->name); > + err = -EINVAL; > + break; > + } > + } > + > + intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL); > + intel_gt_pm_put(gt); > + > + return err; > +} > + > static int live_gt_resume(void *arg) > { > struct intel_gt *gt = arg; > @@ -52,6 +164,7 @@ static int live_gt_resume(void *arg) > int intel_gt_pm_live_selftests(struct drm_i915_private *i915) > { > static const struct i915_subtest tests[] = { > + SUBTEST(live_gt_clocks), > SUBTEST(live_rc6_manual), > SUBTEST(live_rps_clock_interval), > SUBTEST(live_rps_control), > -- > 2.20.1 -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
