Quoting Ville Syrjala (2020-03-02 14:39:38)
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Bunch of places use a 64bit divisor needlessly. Switch
> to 32bit divisor.
>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_perf.c | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 2334c45f1d08..716fe6e4e56c 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1667,10 +1667,9 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
> struct drm_i915_gem_object *bo;
> struct i915_vma *vma;
> const u64 delay_ticks = 0xffffffffffffffff -
> - DIV64_U64_ROUND_UP(
> - atomic64_read(&stream->perf->noa_programming_delay) *
> - RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
> - 1000000ull);
> + DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
> + RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
> + 1000000);
> const u32 base = stream->engine->mmio_base;
> #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
> u32 *batch, *ts0, *cs, *jump;
> @@ -3467,8 +3466,8 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
>
> static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
> {
> - return div64_u64(1000000000ULL * (2ULL << exponent),
> - 1000ULL * RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
> + return div_u64(1000000 * (2ULL << exponent),
> + RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
> }
Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
-Chris
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