Quoting Mika Kuoppala (2020-05-11 17:08:03) > We have problems of tgl not seeing a valid pte entry > when iommu is enabled. Add heavy handed flushing > of entry modification by flushing the cpu, cacheline > and then wcb. This forces the pte out to main memory > past this point regarless of promises of coherency. > > This is an evolution of an experimental patch from > Chris Wilson of adding wmb for coherent partners, > by adding a clflush to force the cache->memory step. > > Testcase: igt/gem_exec_fence/parallel > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> Not only does it help tgl, but it is also helping with a coherency problem on Braswell. We see similar problems on gen9 and icl, and I have a trybot run to see if it helps with those. As it is helping with multiple platforms and diverse symptoms, even if we can't explain why it helps, it is. That makes it prudent to apply to improve the baseline and work from there. Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
