Re: [PATCH v5] drm/i915/dsb: Pre allocate and late cleanup of cmd buffer

["Manna, Animesh" <animesh.manna@xxxxxxxxx>]

On 08-05-2020 16:44, Maarten Lankhorst wrote:
> Op 06-05-2020 om 15:11 schreef Animesh Manna:
> > Pre-allocate command buffer in atomic_commit using intel_dsb_prepare
> > function which also includes pinning and map in cpu domain.
> >
> > No change is dsb write/commit functions.
> >
> > Now dsb get/put function is refactored and currently used only for
> > reference counting. Below dsb api added to do respective job
> > mentioned below.
> >
> > intel_dsb_prepare - Allocate, pin and map the buffer.
> > intel_dsb_cleanup - Unpin and release the gem object.
> >
> > RFC: Initial patch for design review.
> > v2: included _init() part in _prepare(). [Daniel, Ville]
> > v3: dsb_cleanup called after cleanup_planes. [Daniel]
> > v4: dsb structure is moved to intel_crtc_state from intel_crtc. [Maarten]
> > v5: dsb get/put/ref-count mechanism removed. [Maarten]
> >
> > Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> > Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> > Cc: Daniel Vetter <daniel.vetter@xxxxxxxx>
> > Acked-by: Daniel Vetter <daniel.vetter@xxxxxxxx>
> > Signed-off-by: Animesh Manna <animesh.manna@xxxxxxxxx>
> > ---
> >   drivers/gpu/drm/i915/display/intel_color.c    |  27 ++-
> >   drivers/gpu/drm/i915/display/intel_display.c  |  60 ++++-
> >   .../drm/i915/display/intel_display_types.h    |   6 +-
> >   drivers/gpu/drm/i915/display/intel_dsb.c      | 207 +++++++++---------
> >   drivers/gpu/drm/i915/display/intel_dsb.h      |   8 +-
> >   5 files changed, 178 insertions(+), 130 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> > index 98ece9cd7cdd..dba820136106 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -717,7 +717,8 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> >   static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
> >   {
> >   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -	struct intel_dsb *dsb = intel_dsb_get(crtc);
> > +	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
> > +	struct intel_dsb *dsb = (struct intel_dsb *)&crtc_state->dsb;
> >   	enum pipe pipe = crtc->pipe;
> >   
> >   	/* Program the max register to clamp values > 1.0. */
> Please pass the crtc_state, as crtc->state should not be used directly.

I am not sure why ivb_load_lut_ext_max() is taking intel_crtc as argument where other load-lut function take crtc-state. Maybe it is done for older platform.

> > @@ -738,8 +739,6 @@ static void ivb_load_lut_ext_max(struct intel_crtc *crtc)
> >   		intel_dsb_reg_write(dsb, PREC_PAL_EXT2_GC_MAX(pipe, 2),
> >   				    1 << 16);
> >   	}
> > -
> > -	intel_dsb_put(dsb);
> >   }
> >   
> >   static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
> > @@ -900,14 +899,13 @@ icl_load_gcmax(const struct intel_crtc_state *crtc_state,
> >   	       const struct drm_color_lut *color)
> >   {
> >   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > -	struct intel_dsb *dsb = intel_dsb_get(crtc);
> > +	struct intel_dsb *dsb = (struct intel_dsb *)&crtc_state->dsb;
> Why the cast? Unconstify crtc_state as it's obviously not const any more.

Dsb cmd buffer filling is done in load_lut function, so need to unconstify. Otherwise throwing warning during compilation.

> >   	enum pipe pipe = crtc->pipe;
> >   
> >   	/* FIXME LUT entries are 16 bit only, so we can prog 0xFFFF max */
> >   	intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 0), color->red);
> >   	intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 1), color->green);
> >   	intel_dsb_reg_write(dsb, PREC_PAL_GC_MAX(pipe, 2), color->blue);
> > -	intel_dsb_put(dsb);
> >   }
> >   
> >   static void
> > @@ -916,7 +914,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
> >   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
> >   	const struct drm_color_lut *lut = blob->data;
> > -	struct intel_dsb *dsb = intel_dsb_get(crtc);
> > +	struct intel_dsb *dsb = (struct intel_dsb *)&crtc_state->dsb;
> Same.

Need to unconstify to fill the dsb buffer.

> >   	enum pipe pipe = crtc->pipe;
> >   	int i;
> >   
> > @@ -938,8 +936,6 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
> >   		intel_dsb_indexed_reg_write(dsb, PREC_PAL_MULTI_SEG_DATA(pipe),
> >   					    ilk_lut_12p4_udw(entry));
> >   	}
> > -
> > -	intel_dsb_put(dsb);
> >   }
> >   
> >   static void
> > @@ -949,7 +945,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
> >   	const struct drm_property_blob *blob = crtc_state->hw.gamma_lut;
> >   	const struct drm_color_lut *lut = blob->data;
> >   	const struct drm_color_lut *entry;
> > -	struct intel_dsb *dsb = intel_dsb_get(crtc);
> > +	struct intel_dsb *dsb = (struct intel_dsb *)&crtc_state->dsb;
> >   	enum pipe pipe = crtc->pipe;
> >   	int i;
> >   
> > @@ -996,14 +992,22 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
> >   	entry = &lut[256 * 8 * 128];
> >   	icl_load_gcmax(crtc_state, entry);
> >   	ivb_load_lut_ext_max(crtc);
> > -	intel_dsb_put(dsb);
> >   }
> >   
> >   static void icl_load_luts(const struct intel_crtc_state *crtc_state)
> >   {
> >   	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> >   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > -	struct intel_dsb *dsb = intel_dsb_get(crtc);
> > +	struct intel_dsb *dsb = (struct intel_dsb *)&crtc_state->dsb;
> > +
> > +	/*
> > +	 * TODO: Currently dsb buffer filling is done in load_lut() which
> > +	 * can be done much earlier, like initial stage of atomic_commit().
> > +	 * As currently replacing the mmio-write with dsb-write so the same
> > +	 * load_lut() api is used for dsb buffer creation which may not
> > +	 * fit in initial stage. Need to create a separate interface and
> > +	 * a different path in color framework while dealing with dsb.
> > +	 */
> >   
> >   	if (crtc_state->hw.degamma_lut)
> >   		glk_load_degamma_lut(crtc_state);
> > @@ -1022,7 +1026,6 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
> >   	}
> >   
> >   	intel_dsb_commit(dsb);
> > -	intel_dsb_put(dsb);
> >   }
> >   
> >   static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index fd6d63b03489..07670893c1ae 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14873,8 +14873,28 @@ static int intel_atomic_check(struct drm_device *dev,
> >   
> >   static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
> >   {
> > -	return drm_atomic_helper_prepare_planes(state->base.dev,
> > -						&state->base);
> > +	struct intel_crtc_state *crtc_state;
> > +	struct intel_crtc *crtc;
> > +	int i, ret;
> > +
> > +	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
> > +	if (ret < 0)
> > +		return ret;
> > +
> > +	/*
> > +	 * In case of DSB buffer creation failure register programming will be
> > +	 * done by mmio and erroneous path will be handled by dsp-write api.
> > +	 */
> > +	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> > +		bool mode_changed = needs_modeset(crtc_state);
> > +
> > +		if (mode_changed || crtc_state->update_pipe ||
> > +		    crtc_state->uapi.color_mgmt_changed) {
> > +			intel_dsb_prepare(crtc_state);
> > +		}
> > +	}
> > +
> > +	return 0;
> >   }
> >   
> >   u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
> > @@ -15327,15 +15347,39 @@ static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_stat
> >   		    &wait_reset);
> >   }
> >   
> > +static void intel_cleanup_dsbs(struct intel_atomic_state *state)
> > +{
> > +	struct intel_crtc_state *crtc_state, *old_crtc_state, *new_crtc_state;
> > +	struct intel_crtc *crtc;
> > +	int i;
> > +
> > +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> > +		bool mode_changed;
> > +
> > +		if (old_crtc_state == crtc->config)
> > +			crtc_state = new_crtc_state;
> > +		else
> > +			crtc_state = old_crtc_state;
> > +
> > +		mode_changed = needs_modeset(crtc_state);
> > +		if (mode_changed || crtc_state->update_pipe ||
> > +		    crtc_state->uapi.color_mgmt_changed) {
> > +			intel_dsb_cleanup(crtc_state);
> Just call the cleanup function unconditionally here, the dsb->vma = NULL check is enough.

Ok.

> > +		}
> > +	}
> > +}
> > +
> >   static void intel_atomic_cleanup_work(struct work_struct *work)
> >   {
> > -	struct drm_atomic_state *state =
> > -		container_of(work, struct drm_atomic_state, commit_work);
> > -	struct drm_i915_private *i915 = to_i915(state->dev);
> > +	struct intel_atomic_state *state =
> > +		container_of(work, struct intel_atomic_state, base.commit_work);
> > +	struct drm_i915_private *i915 = to_i915(state->base.dev);
> >   
> > -	drm_atomic_helper_cleanup_planes(&i915->drm, state);
> > -	drm_atomic_helper_commit_cleanup_done(state);
> > -	drm_atomic_state_put(state);
> > +	if (HAS_DSB(i915))
> > +		intel_cleanup_dsbs(state);
> > +	drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
> > +	drm_atomic_helper_commit_cleanup_done(&state->base);
> > +	drm_atomic_state_put(&state->base);
> >   
> >   	intel_atomic_helper_free_state(i915);
> >   }
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 9488449e4b94..805ca774e146 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1078,6 +1078,9 @@ struct intel_crtc_state {
> >   
> >   	/* Only valid on TGL+ */
> >   	enum transcoder mst_master_transcoder;
> > +
> > +	/* For DSB related info */
> > +	struct intel_dsb dsb;
> >   };
> >   
> >   enum intel_pipe_crc_source {
> > @@ -1147,9 +1150,6 @@ struct intel_crtc {
> >   	/* scalers available on this crtc */
> >   	int num_scalers;
> >   
> > -	/* per pipe DSB related info */
> > -	struct intel_dsb dsb;
> > -
> >   #ifdef CONFIG_DEBUG_FS
> >   	struct intel_pipe_crc pipe_crc;
> >   #endif
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
> > index 29fec6a92d17..247fd564d394 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > @@ -34,18 +34,22 @@
> >   #define DSB_BYTE_EN_SHIFT		20
> >   #define DSB_REG_VALUE_MASK		0xfffff
> >   
> > -static bool is_dsb_busy(struct intel_dsb *dsb)
> > +static inline bool is_dsb_busy(struct intel_dsb *dsb)
> >   {
> > -	struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> > +	struct intel_crtc_state *crtc_state =
> > +		container_of(dsb, typeof(*crtc_state), dsb);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >   	enum pipe pipe = crtc->pipe;
> >   
> >   	return DSB_STATUS & intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id));
> >   }
> >   
> > -static bool intel_dsb_enable_engine(struct intel_dsb *dsb)
> > +static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb)
> >   {
> > -	struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> > +	struct intel_crtc_state *crtc_state =
> > +		container_of(dsb, typeof(*crtc_state), dsb);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >   	enum pipe pipe = crtc->pipe;
> >   	u32 dsb_ctrl;
> > @@ -63,9 +67,11 @@ static bool intel_dsb_enable_engine(struct intel_dsb *dsb)
> >   	return true;
> >   }
> >   
> > -static bool intel_dsb_disable_engine(struct intel_dsb *dsb)
> > +static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb)
> >   {
> > -	struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> > +	struct intel_crtc_state *crtc_state =
> > +		container_of(dsb, typeof(*crtc_state), dsb);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >   	enum pipe pipe = crtc->pipe;
> >   	u32 dsb_ctrl;
> > @@ -83,99 +89,6 @@ static bool intel_dsb_disable_engine(struct intel_dsb *dsb)
> >   	return true;
> >   }
> >   
> > -/**
> > - * intel_dsb_get() - Allocate DSB context and return a DSB instance.
> > - * @crtc: intel_crtc structure to get pipe info.
> > - *
> > - * This function provides handle of a DSB instance, for the further DSB
> > - * operations.
> > - *
> > - * Returns: address of Intel_dsb instance requested for.
> > - * Failure: Returns the same DSB instance, but without a command buffer.
> > - */
> > -
> > -struct intel_dsb *
> > -intel_dsb_get(struct intel_crtc *crtc)
> > -{
> > -	struct drm_device *dev = crtc->base.dev;
> > -	struct drm_i915_private *i915 = to_i915(dev);
> > -	struct intel_dsb *dsb = &crtc->dsb;
> > -	struct drm_i915_gem_object *obj;
> > -	struct i915_vma *vma;
> > -	u32 *buf;
> > -	intel_wakeref_t wakeref;
> > -
> > -	if (!HAS_DSB(i915))
> > -		return dsb;
> > -
> > -	if (dsb->refcount++ != 0)
> > -		return dsb;
> > -
> > -	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> > -
> > -	obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
> > -	if (IS_ERR(obj)) {
> > -		drm_err(&i915->drm, "Gem object creation failed\n");
> > -		goto out;
> > -	}
> > -
> > -	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
> > -	if (IS_ERR(vma)) {
> > -		drm_err(&i915->drm, "Vma creation failed\n");
> > -		i915_gem_object_put(obj);
> > -		goto out;
> > -	}
> > -
> > -	buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
> > -	if (IS_ERR(buf)) {
> > -		drm_err(&i915->drm, "Command buffer creation failed\n");
> > -		goto out;
> > -	}
> > -
> > -	dsb->id = DSB1;
> > -	dsb->vma = vma;
> > -	dsb->cmd_buf = buf;
> > -
> > -out:
> > -	/*
> > -	 * On error dsb->cmd_buf will continue to be NULL, making the writes
> > -	 * pass-through. Leave the dangling ref to be removed later by the
> > -	 * corresponding intel_dsb_put(): the important error message will
> > -	 * already be logged above.
> > -	 */
> > -
> > -	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> > -
> > -	return dsb;
> > -}
> > -
> > -/**
> > - * intel_dsb_put() - To destroy DSB context.
> > - * @dsb: intel_dsb structure.
> > - *
> > - * This function destroys the DSB context allocated by a dsb_get(), by
> > - * unpinning and releasing the VMA object associated with it.
> > - */
> > -
> > -void intel_dsb_put(struct intel_dsb *dsb)
> > -{
> > -	struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> > -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > -
> > -	if (!HAS_DSB(i915))
> > -		return;
> > -
> > -	if (drm_WARN_ON(&i915->drm, dsb->refcount == 0))
> > -		return;
> > -
> > -	if (--dsb->refcount == 0) {
> > -		i915_vma_unpin_and_release(&dsb->vma, I915_VMA_RELEASE_MAP);
> > -		dsb->cmd_buf = NULL;
> > -		dsb->free_pos = 0;
> > -		dsb->ins_start_offset = 0;
> > -	}
> > -}
> > -
> >   /**
> >    * intel_dsb_indexed_reg_write() -Write to the DSB context for auto
> >    * increment register.
> > @@ -192,7 +105,9 @@ void intel_dsb_put(struct intel_dsb *dsb)
> >   void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
> >   				 u32 val)
> >   {
> > -	struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> > +	struct intel_crtc_state *crtc_state =
> > +		container_of(dsb, typeof(*crtc_state), dsb);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >   	u32 *buf = dsb->cmd_buf;
> >   	u32 reg_val;
> > @@ -267,7 +182,9 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
> >    */
> >   void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
> >   {
> > -	struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> > +	struct intel_crtc_state *crtc_state =
> > +		container_of(dsb, typeof(*crtc_state), dsb);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >   	u32 *buf = dsb->cmd_buf;
> >   
> > @@ -297,7 +214,9 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val)
> >    */
> >   void intel_dsb_commit(struct intel_dsb *dsb)
> >   {
> > -	struct intel_crtc *crtc = container_of(dsb, typeof(*crtc), dsb);
> > +	struct intel_crtc_state *crtc_state =
> > +		container_of(dsb, typeof(*crtc_state), dsb);
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> Please pass crtc_state instead to all functions above. :)

Yes, can be done.

> >   	struct drm_device *dev = crtc->base.dev;
> >   	struct drm_i915_private *dev_priv = to_i915(dev);
> >   	enum pipe pipe = crtc->pipe;
> > @@ -343,3 +262,87 @@ void intel_dsb_commit(struct intel_dsb *dsb)
> >   	dsb->ins_start_offset = 0;
> >   	intel_dsb_disable_engine(dsb);
> >   }
> > +
> > +/**
> > + * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer.
> > + * @crtc_state: intel_crtc_state structure to prepare associated dsb instance.
> > + *
> > + * This function prepare the command buffer which is used to store dsb
> > + * instructions with data.
> > + */
> > +
> > +void intel_dsb_prepare(struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > +	struct intel_dsb *dsb = &crtc_state->dsb;
> > +	struct drm_i915_gem_object *obj;
> > +	struct i915_vma *vma;
> > +	u32 *buf;
> > +	intel_wakeref_t wakeref;
> > +
> > +	if (!HAS_DSB(i915) || dsb->cmd_buf)
> > +		return;
> > +
> > +	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
> > +
> > +	obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE);
> > +	if (IS_ERR(obj)) {
> > +		drm_err(&i915->drm, "Gem object creation failed\n");
> > +		goto out;
> > +	}
> > +
> > +	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
> > +	if (IS_ERR(vma)) {
> > +		drm_err(&i915->drm, "Vma creation failed\n");
> > +		i915_gem_object_put(obj);
> > +		goto out;
> > +	}
> > +
> > +	buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC);
> > +	if (IS_ERR(buf)) {
> > +		drm_err(&i915->drm, "Command buffer creation failed\n");
> > +		goto out;
> > +	}
> > +
> > +	dsb->id = DSB1;
> > +	dsb->vma = vma;
> > +	dsb->cmd_buf = buf;
> > +
> > +out:
> > +	/*
> > +	 * On error dsb->cmd_buf will continue to be NULL, making the writes
> > +	 * pass-through. Leave the dangling ref to be removed later by the
> > +	 * corresponding intel_dsb_put(): the important error message will
> > +	 * already be logged above.
> > +	 */
> > +
> > +	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
> > +}
> > +
> > +/**
> > + * intel_dsb_cleanup() - To cleanup DSB context.
> > + * @crtc_state: intel_crtc_state structure to cleanup associated dsb instance.
> > + *
> > + * This function cleanup the DSB context by unpinning and releasing
> > + * the VMA object associated with it.
> > + */
> > +
> > +void intel_dsb_cleanup(struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_dsb *dsb = &crtc_state->dsb;
> > +	struct i915_vma *p_vma;
> > +
> > +	if (dsb->vma) {
> > +		p_vma = fetch_and_zero(&dsb->vma);
> > +		if (p_vma) {
> > +			i915_vma_unpin(p_vma);
> > +			i915_gem_object_unpin_map(p_vma->obj);
> > +			i915_gem_object_put(p_vma->obj);
> > +		}
> > +		dsb->vma = NULL;
> > +		dsb->cmd_buf = NULL;
> > +		dsb->free_pos = 0;
> > +		dsb->ins_start_offset = 0;
> > +	}
> > +}
> I would simplify cleanup to vma = fetch_and_zero(&dsb->vma); if (!vma) return; and then only call the vma/gem functions to clean up. No need to fix the other stuff here as the struct is being freed.

Sure .. do you mean like below?

void intel_dsb_cleanup(struct intel_crtc_state *crtc_state)
{
	struct intel_dsb *dsb = &crtc_state->dsb;
	struct i915_vma *p_vma = fetch_and_zero(&dsb->vma);

	if (!p_vma)
		return;

	i915_vma_unpin(p_vma);
	i915_gem_object_unpin_map(p_vma->obj);
	i915_gem_object_put(p_vma->obj);
	dsb->vma = NULL;
	dsb->cmd_buf = NULL;
	dsb->free_pos = 0;
	dsb->ins_start_offset = 0;
}

> Could probably drop the fetch_and_zero as well, but wouldn't hurt for paranoia. :)
>
> Otherwise looks good now, only few tweaks are needed for the patch to be ready!

Thanks for review. :)

Regards,
Animesh

> ~Maarten
>
>
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
> > index 395ef9ce558e..3a20a4388b9a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> > @@ -10,7 +10,7 @@
> >   
> >   #include "i915_reg.h"
> >   
> > -struct intel_crtc;
> > +struct intel_crtc_state;
> >   struct i915_vma;
> >   
> >   enum dsb_id {
> > @@ -22,7 +22,6 @@ enum dsb_id {
> >   };
> >   
> >   struct intel_dsb {
> > -	long refcount;
> >   	enum dsb_id id;
> >   	u32 *cmd_buf;
> >   	struct i915_vma *vma;
> > @@ -41,9 +40,8 @@ struct intel_dsb {
> >   	u32 ins_start_offset;
> >   };
> >   
> > -struct intel_dsb *
> > -intel_dsb_get(struct intel_crtc *crtc);
> > -void intel_dsb_put(struct intel_dsb *dsb);
> > +void intel_dsb_prepare(struct intel_crtc_state *crtc_state);
> > +void intel_dsb_cleanup(struct intel_crtc_state *crtc_state);
> >   void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val);
> >   void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg,
> >   				 u32 val);
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