On Thu, Apr 30, 2020 at 03:58:21PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> GLK wants the +1 adjustement for the "blocks per line" value
> for x-tile/y-tile, just like cnl+.
>
> Also the x-tile and linear cases are almost identical. The only
> difference is this +1 which is always done for glk+, and only
> done for linear on skl/bxt. Let's unify it to a single branch
> with a special case for the +1, just like we do for y-tile.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bfb180fe8047..65a3236ce277 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4810,7 +4810,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, u32 pixel_rate,
> wm_intermediate_val = latency * pixel_rate * cpp;
> ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size);
>
> - if (INTEL_GEN(dev_priv) >= 10)
> + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> ret = add_fixed16_u32(ret, 1);
>
> return ret;
> @@ -4945,18 +4945,19 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
> wp->y_min_scanlines,
> wp->dbuf_block_size);
>
> - if (INTEL_GEN(dev_priv) >= 10)
> + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> interm_pbpl++;
>
> wp->plane_blocks_per_line = div_fixed16(interm_pbpl,
> wp->y_min_scanlines);
> - } else if (wp->x_tiled && IS_GEN(dev_priv, 9)) {
> - interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> - wp->dbuf_block_size);
> - wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
> } else {
> interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line,
> - wp->dbuf_block_size) + 1;
> + wp->dbuf_block_size);
> +
> + if (!wp->x_tiled ||
> + INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> + interm_pbpl++;
> +
Is it so that we want +1 here only for x-tile,y-tile for GLK?
Because I guess if you have linear mapping and GLK, this will do +1 as well.
With this clarified,
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl);
> }
>
> --
> 2.24.1
>
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