On Tue, May 05, 2020 at 02:01:16PM +0300, Ville Syrjälä wrote:
> On Tue, May 05, 2020 at 01:42:46PM +0300, Ville Syrjälä wrote:
> > On Tue, May 05, 2020 at 01:22:43PM +0300, Stanislav Lisovskiy wrote:
> > > Introduce platform dependent SAGV checking in
> > > combination with bandwidth state pipe SAGV mask.
> > >
> > > v2, v3, v4, v5, v6: Fix rebase conflict
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
> > > ---
> > > drivers/gpu/drm/i915/intel_pm.c | 30 ++++++++++++++++++++++++++++--
> > > 1 file changed, 28 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index da567fac7c93..c7d726a656b2 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -3853,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > return true;
> > > }
> > >
> > > +static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > +{
> > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > + /*
> > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > + * more then one pipe enabled
> > > + */
> > > + if (hweight8(state->active_pipes) > 1)
> > > + return false;
> >
> > That stuff should no longer be here since we now have it done properly
> > in intel_can_eanble_sagv().
> >
> > > +
> > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > +}
> > > +
> > > +static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > +{
> > > + return intel_crtc_can_enable_sagv(crtc_state);
> > > +}
> >
> > This looks the wrong way around. IMO intel_crtc_can_enable_sagv()
> > should rather call the skl vs. icl variants as needed. Although we
> > don't yet have the icl variant so the oerdering of the patches is
> > a bit weird.
>
> Do we even need an icl variant actually? Does it use the skl or tgl
> way of checking for sagv yes vs. no?
As I undestand icl implementation should be pretty much the same as
skl, except that icl doesn't have this one active pipe limitation
thing.
Stan
>
> >
> > > +
> > > bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > {
> > > if (bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
> > > @@ -3863,22 +3881,30 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > >
> > > static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > {
> > > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > int ret;
> > > struct intel_crtc *crtc;
> > > - struct intel_crtc_state *new_crtc_state;
> > > + const struct intel_crtc_state *new_crtc_state;
> > > struct intel_bw_state *new_bw_state = NULL;
> > > const struct intel_bw_state *old_bw_state = NULL;
> > > int i;
> > >
> > > for_each_new_intel_crtc_in_state(state, crtc,
> > > new_crtc_state, i) {
> > > + bool can_sagv;
> > > +
> > > new_bw_state = intel_atomic_get_bw_state(state);
> > > if (IS_ERR(new_bw_state))
> > > return PTR_ERR(new_bw_state);
> > >
> > > old_bw_state = intel_atomic_get_old_bw_state(state);
> > >
> > > - if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > + if (INTEL_GEN(dev_priv) >= 11)
> > > + can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
> > > + else
> > > + can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
> > > +
> > > + if (can_sagv)
> > > new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > else
> > > new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > --
> > > 2.24.1.485.gad05a3d8e5
> >
> > --
> > Ville Syrjälä
> > Intel
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
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