On Monday, May 4, 2020 5:01:46 PM PDT D Scott Phillips wrote: > Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12 > pipe_control commands. HDC Pipeline flush actually resides in > dword 0, and the bit we were setting in dword 1 was Indirect State > Pointers Disable, which invalidates indirect state in the render > context. This causes failures for userspace, as things like push > constant state gets invalidated. > > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Signed-off-by: D Scott Phillips <d.scott.phillips@xxxxxxxxx> > --- > drivers/gpu/drm/i915/gt/intel_engine.h | 23 +++++++++++++++++------ > drivers/gpu/drm/i915/gt/intel_lrc.c | 11 ++++++----- > 2 files changed, 23 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h > index 19d0b8830905..8338be338ec8 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h > @@ -241,19 +241,24 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); > void intel_engine_print_breadcrumbs(struct intel_engine_cs *engine, > struct drm_printer *p); > > -static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) > +static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset) Great find! It looks like HDC_PIPELINE_FLUSH moved from bit 41 to bit 9 even on Icelake / Gen11 - so it might make sense to call this gen11_emit_pipe_control() and use it on the Icelake functions. That said, i915 never sets HDC_PIPELINE_FLUSH until Gen12, so we don't actually have a bug to fix on Icelake today. But if someone started trying to set it on Gen11, we would have a bug - hence the suggestion. With or without any changes, Reviewed-by: Kenneth Graunke <kenneth@xxxxxxxxxxxxx> and thanks so much for tracking this down!
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