Quoting Lionel Landwerlin (2020-05-04 12:12:48)
> +static int oa_get_render_ctx_ids(struct i915_perf_stream *stream)
> {
> struct intel_context *ce;
> + int i, err = 0;
> + u32 n_allocated_ctxs = 0;
>
> - ce = fetch_and_zero(&stream->pinned_ctx);
> - if (ce) {
> - ce->tag = 0; /* recomputed on next submission after parking */
> - intel_context_unpin(ce);
> + stream->ctx_id_mask = get_ctx_id_mask(stream->engine);
> +
> + for (i = 0; i < stream->n_ctxs; i++) {
> + struct i915_gem_context *ctx = stream->ctxs[i];
> + struct i915_gem_engines_iter it;
> +
> + for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> + if (ce->engine != stream->engine) /* first match! */
> + continue;
> +
> + /*
> + * As the ID is the gtt offset of the context's vma we
> + * pin the vma to ensure the ID remains fixed.
> + */
> + err = intel_context_pin(ce);
> + if (err) {
> + i915_gem_context_unlock_engines(ctx);
> + break;
> + }
> +
> + if (stream->n_pinned_ctxs >= n_allocated_ctxs) {
> + u32 new_allocated_len = max(n_allocated_ctxs * 2, 2u);
> + struct i915_perf_context_detail *new_ctxs =
> + krealloc(stream->pinned_ctxs,
> + sizeof(*stream->pinned_ctxs) *
> + new_allocated_len,
> + GFP_KERNEL);
> +
> + if (!new_ctxs) {
> + err = -ENOMEM;
> + break;
> + }
> +
> + n_allocated_ctxs = new_allocated_len;
> + stream->pinned_ctxs = new_ctxs;
> + }
> +
> + stream->pinned_ctxs[stream->n_pinned_ctxs].ce = ce;
> + stream->pinned_ctxs[stream->n_pinned_ctxs].id = get_ctx_id(ce, i);
> +
> + drm_dbg(&stream->perf->i915->drm,
> + "filtering on ctx_id%i=0x%x ctx_id_mask=0x%x\n",
> + i, stream->pinned_ctxs[i].id, stream->ctx_id_mask);
> +
> + ce->tag = stream->pinned_ctxs[stream->n_pinned_ctxs].id;
> +
> + stream->n_pinned_ctxs++;
> + }
> + i915_gem_context_unlock_engines(ctx);
> + if (err)
> + goto err;
> }
For each GEM context handle the user supplied, match on all HW contexts.
Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
-Chris
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