Quoting Andi Shyti (2020-04-24 13:50:40) > Hi Chris, > > On Wed, Apr 22, 2020 at 01:17:01AM +0100, Chris Wilson wrote: > > The RPS DOWN_TIMEOUT interrupt is signaled after a period of rc6, and > > upon receipt of that interrupt we reprogram the GPU clocks down to the > > next idle notch [to help convserve power during rc6]. However, on > > execlists, we benefit from soft-rc6 immediately parking the GPU and > > setting idle frequencies upon idling [within a jiffie], and here the > > interrupt prevents us from restarting from our last frequency. > > > > In the process, we can simply opt for a static pm_events mask and rely > > on the enable/disable interrupts to flush the worker on parking. > > > > This will reduce the amount of oscillation observed during steady > > workloads with microsleeps, as each time the rc6 timeout occurs we > > immediately follow with a waitboost for a dropped frame. > > > > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > > --- > > drivers/gpu/drm/i915/gt/intel_rps.c | 41 +++++++++++++---------------- > > 1 file changed, 18 insertions(+), 23 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c > > index 4dcfae16a7ce..785cd58fba76 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > > @@ -57,7 +57,7 @@ static u32 rps_pm_mask(struct intel_rps *rps, u8 val) > > if (val < rps->max_freq_softlimit) > > mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; > > > > - mask &= READ_ONCE(rps->pm_events); > > + mask &= rps->pm_events; > > we are giving up the read/write ordering here because we thing > that removing the down interval we won't have anymore > inconsistent reads? Correct. Since we are now only setting rps->pm_events during initialisation, it remains constant at runtime, and we do not need to worry about read tearing or repeated reads. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
