Due to the latency from impedance mismatch on memory access, as the GPU
gets faster we need to increase the frequency of the ring to offset.
In effect, we are fixing the topmost frequency selection, and scaling
down faster, so that at low frequencies we will be using lower ring
frequencies and conserving power (and in the process make the scaling
fairer, and aim for a linear increase in performance with frequency).
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/gt/intel_llc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_llc.c b/drivers/gpu/drm/i915/gt/intel_llc.c
index e3f637b3650e..27196c303cbe 100644
--- a/drivers/gpu/drm/i915/gt/intel_llc.c
+++ b/drivers/gpu/drm/i915/gt/intel_llc.c
@@ -89,7 +89,7 @@ static void calc_ia_freq(struct intel_llc *llc,
* ring_freq = 2 * GT. ring_freq is in 100MHz units
* No floor required for ring frequency on SKL.
*/
- ring_freq = gpu_freq;
+ ring_freq = consts->max_gpu_freq - mult_frac(diff, 5, 4);
} else if (INTEL_GEN(i915) >= 8) {
/* max(2 * GT, DDR). NB: GT is 50MHz units */
ring_freq = max(consts->min_ring_freq, gpu_freq);
--
2.20.1
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