On Tue, 2020-04-14 at 14:11 -0700, Matt Roper wrote:
> Even though the bspec is missing gen12 register details for the MCR
> selector register (0xFDC), this is confirmed by hardware folks to be
> a
> mistake; the register does exist and we do indeed need to steer
> multicast register reads to an appropriate instance the same as we
> did
> on gen11.
>
> Note that despite the lack of documentation we were still using the
> MCR
> selector to read INSTDONE and such in read_subslice_reg() too.
>
Reviewed-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Cc: Matt Atwood <matthew.s.atwood@xxxxxxxxx>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 5b1a03d2fd25..adddc5c93b48 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -943,6 +943,8 @@ icl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> static void
> tgl_gt_workarounds_init(struct drm_i915_private *i915, struct
> i915_wa_list *wal)
> {
> + wa_init_mcr(i915, wal);
> +
> /* Wa_1409420604:tgl */
> if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> wa_write_or(wal,
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