Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_pm.c | 71 ++++++++++++++++++++++++++-------
1 file changed, 57 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 41305abad179..026d48209cc9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3761,8 +3761,23 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state = NULL;
- if (!intel_can_enable_sagv(state)) {
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ * This is different from situation when we have SAGV but just can't
+ * afford it due to DBuf limitation - in case if SAGV is completely
+ * disabled in a BIOS, we are not even allowed to send a PCode request,
+ * as it will throw an error. So have to check it here.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (!intel_can_enable_sagv(new_bw_state)) {
intel_disable_sagv(dev_priv);
return;
}
@@ -3771,8 +3786,23 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state = NULL;
- if (intel_can_enable_sagv(state)) {
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ * This is different from situation when we have SAGV but just can't
+ * afford it due to DBuf limitation - in case if SAGV is completely
+ * disabled in a BIOS, we are not even allowed to send a PCode request,
+ * as it will throw an error. So have to check it here.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (intel_can_enable_sagv(new_bw_state)) {
intel_enable_sagv(dev_priv);
return;
}
@@ -3780,7 +3810,6 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
- struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct intel_plane *plane;
@@ -3790,13 +3819,6 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
if (!crtc_state->hw.active)
return true;
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
-
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
pipe_name(crtc->pipe));
@@ -3835,6 +3857,23 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
return true;
}
+static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
+ /*
+ * SKL+ workaround: bspec recommends we disable SAGV when we have
+ * more then one pipe enabled
+ */
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
+static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
@@ -3846,9 +3885,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *crtc_state;
- enum pipe pipe;
- struct intel_crtc_state *new_crtc_state;
+ const struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
@@ -3858,6 +3895,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
for_each_new_intel_crtc_in_state(state, crtc,
new_crtc_state, i) {
+ bool can_sagv;
new_bw_state = intel_atomic_get_bw_state(state);
if (IS_ERR(new_bw_state))
@@ -3865,7 +3903,12 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
old_bw_state = intel_atomic_get_old_bw_state(state);
- if (intel_crtc_can_enable_sagv(new_crtc_state))
+ if (INTEL_GEN(dev_priv) >= 11)
+ can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
+ else
+ can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
+
+ if (can_sagv)
new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
else
new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
--
2.24.1.485.gad05a3d8e5
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