For our gpu relocs, on the older gen 4 and 5 devices, we must use a privileged buffer for MI_STORE_DWORD_IMM. This also presumes that we operate from the global GTT, for consistency we should tell i915_vma_pin() that it will be used with the global address. While there is only the single GTT available for these devices, so it does not change the actual GTT used for pinning. Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c index 005b42acf7c8..f6cf8ff7033f 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c @@ -1202,6 +1202,7 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, struct intel_engine_pool_node *pool; struct i915_request *rq; struct i915_vma *batch; + u32 flags; u32 *cmd; int err; @@ -1224,7 +1225,11 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, goto err_unmap; } - err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK); + flags = PIN_USER | PIN_NOEVICT | PIN_NONBLOCK; + if (cache->gen <= 5) + flags |= PIN_GLOBAL; + + err = i915_vma_pin(batch, 0, 0, flags); if (err) goto err_unmap; @@ -1244,7 +1249,8 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, err = eb->engine->emit_bb_start(rq, batch->node.start, PAGE_SIZE, - cache->gen > 5 ? 0 : I915_DISPATCH_SECURE); + flags & PIN_GLOBAL ? + I915_DISPATCH_SECURE : 0); if (err) goto skip_request; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
