On Thu, 2020-03-12 at 15:07 -0700, Lucas De Marchi wrote:
> On Wed, Mar 04, 2020 at 05:04:52PM -0800, Lucas De Marchi wrote:
> > On Wed, Mar 4, 2020 at 2:33 PM Caz Yokoyama <caz.yokoyama@xxxxxxxxx
> > > wrote:
> > > This reverts commit 36a6b5d964d995b536b1925ec42052ee40ba92c4.
> > > Fixes: 36a6b5d964d9 ("drm/i915/tgl: Add extra hdc flush
> > > workaround")
> > >
> > > The commit takes care Wa_1604544889 which was fixed on a0
> > > stepping based on
> > > a0 replan. So no SW workaround is required on any stepping now.
> > >
> > > Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> > > Signed-off-by: Caz Yokoyama <caz.yokoyama@xxxxxxxxx>
> >
> > You didn't add what the reviewers asked for. Please go back to the
> > reviews and check that you
> > still have things to change in this commit in order to add his r-b.
> > Also check what José said.
>
> I think we can live without the comment José asked for. So only
> additional thing still wrong here is the "Fixes" line. It needs to be
> together with the other trailers. We can do that while applying.
Fixes line moved and pushed, thanks for the patch.
>
> thanks
>
> Lucas De Marchi
>
> >
> > Lucas De Marchi
> >
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_lrc.c | 20 --------------------
> > > 1 file changed, 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > index b9b3f78f1324..f9425e5ed7ea 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > > @@ -4145,26 +4145,6 @@ static int gen12_emit_flush_render(struct
> > > i915_request *request,
> > >
> > > *cs++ = preparser_disable(false);
> > > intel_ring_advance(request, cs);
> > > -
> > > - /*
> > > - * Wa_1604544889:tgl
> > > - */
> > > - if (IS_TGL_REVID(request->i915, TGL_REVID_A0,
> > > TGL_REVID_A0)) {
> > > - flags = 0;
> > > - flags |= PIPE_CONTROL_CS_STALL;
> > > - flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
> > > -
> > > - flags |= PIPE_CONTROL_STORE_DATA_INDEX;
> > > - flags |= PIPE_CONTROL_QW_WRITE;
> > > -
> > > - cs = intel_ring_begin(request, 6);
> > > - if (IS_ERR(cs))
> > > - return PTR_ERR(cs);
> > > -
> > > - cs = gen8_emit_pipe_control(cs, flags,
> > > - LRC_PPHWSP_SC
> > > RATCH_ADDR);
> > > - intel_ring_advance(request, cs);
> > > - }
> > > }
> > >
> > > return 0;
> > > --
> > > 2.21.0.5.gaeb582a983
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
> > --
> > Lucas De Marchi
> _______________________________________________
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