Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes:
> Due to the ordering of cmpxchg()/dma_fence_signal() inside node_retire(),
> we must also use the xchg() as our primary memory barrier to flush the
> outstanding callbacks after expected completion of the i915_active.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Reviewed-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/selftests/i915_active.c | 29 ++++++++++++++------
> 1 file changed, 21 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c b/drivers/gpu/drm/i915/selftests/i915_active.c
> index 3a37c67ab6c4..68bbb1580162 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_active.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_active.c
> @@ -311,20 +311,33 @@ static void spin_unlock_wait(spinlock_t *lock)
> spin_unlock_irq(lock);
> }
>
> +static void active_flush(struct i915_active *ref,
> + struct i915_active_fence *active)
> +{
> + struct dma_fence *fence;
> +
> + fence = xchg(__active_fence_slot(active), NULL);
> + if (!fence)
> + return;
> +
> + spin_lock_irq(fence->lock);
> + __list_del_entry(&active->cb.node);
> + spin_unlock_irq(fence->lock); /* serialise with fence->cb_list */
> + atomic_dec(&ref->count);
> +
> + GEM_BUG_ON(!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags));
> +}
> +
> void i915_active_unlock_wait(struct i915_active *ref)
> {
> if (i915_active_acquire_if_busy(ref)) {
> struct active_node *it, *n;
>
> + /* Wait for all active callbacks */
> rcu_read_lock();
> - rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node) {
> - struct dma_fence *f;
> -
> - /* Wait for all active callbacks */
> - f = rcu_dereference(it->base.fence);
> - if (f)
> - spin_unlock_wait(f->lock);
> - }
> + active_flush(ref, &ref->excl);
> + rbtree_postorder_for_each_entry_safe(it, n, &ref->tree, node)
> + active_flush(ref, &it->base);
> rcu_read_unlock();
>
> i915_active_release(ref);
> --
> 2.25.1
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