On Tue, Mar 03, 2020 at 10:29:04AM -0800, Matt Roper wrote: > intel_ddi_clock_get() tests the DPLL ID against DPLL_ID_ICL_TBTPLL (2) > to determine whether to try to descend into a TBT-specific handler. > However this test will also be true when DPLL4 on EHL is used since that > shares the same DPLL ID (2). > > Add an extra check to ensure the PHY is actually a Type-C PHY before > descending into the TBT handling. This should ensure EHL still takes > the correct code path and somewhat future-proof the code as well. > > Cc: José Roberto de Souza <jose.souza@xxxxxxxxx> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1369 Fixes: 45e4728b87ad ("drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c") Cc: Imre Deak <imre.deak@xxxxxxxxx> I think. Matt > Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index 284219da7df8..aa3cc42b0eb9 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -1376,8 +1376,9 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); > > - if (INTEL_GEN(dev_priv) >= 11 && > + if (INTEL_GEN(dev_priv) >= 11 && intel_phy_is_tc(dev_priv, phy) && > intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == > DPLL_ID_ICL_TBTPLL) > pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, > -- > 2.24.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
