From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
On ilk the UDW of TIMESTAMP increments every 1000 ns,
LDW is mbz. In order to represent cs_timestamp_frequency_hz
for that we'd need 52 bits, but we only have 32 bits.
Even worse most things want to only deak with the low
32 bits of timestamp. So let's just set up cs_timestamp_frequency_hz
as if we only had the UDW.
On ctg/elk 63:20 of TIMESTAMP increments every 1/4 ns, 19:0
are mbz. To make life simpler let's ignore the LDW and set up
cs_timestamp_frequency_hz based on the UDW only (increments
evert 1024 ns).
Cc: Lionel Landwerlin <lionel.g.landwerlin@xxxxxxxxx>
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_device_info.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 32733535964d..b756e8fb7682 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -739,7 +739,10 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
u32 f19_2_mhz = 19200000;
u32 f24_mhz = 24000000;
- if (INTEL_GEN(dev_priv) <= 4) {
+ if (INTEL_GEN(dev_priv) < 4)
+ return 0;
+
+ if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
/* PRMs say:
*
* "The value in this register increments once every 16
@@ -747,6 +750,20 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
* (“CLKCFG”) MCHBAR register)
*/
return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16;
+ } else if (IS_G4X(dev_priv)) {
+ /*
+ * 63:20 increments every 1/4 ns
+ * 19:0 mbz
+ *
+ * -> 63:32 increments every 1024 ns
+ */
+ return 1000000000 / 1024;
+ } else if (IS_GEN(dev_priv, 5)) {
+ /*
+ * 63:32 increments every 1000 ns
+ * 31:0 mbz
+ */
+ return 1000000000 / 1000;
} else if (INTEL_GEN(dev_priv) <= 8) {
/* PRMs say:
*
--
2.24.1
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